Commit 3a3be8bb authored by Yang Wang's avatar Yang Wang Committed by Alex Deucher
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drm/amdgpu: refine gfx8 firmware loading 



refine gfx8 firmware loading

Signed-off-by: default avatarYang Wang <kevinyang.wang@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9d308e32

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

+33 −36
Original line number Diff line number Diff line
@@ -939,7 +939,6 @@ static void gfx_v8_0_free_microcode(struct amdgpu_device *adev) 
static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)

{

	const char *chip_name;

	char fw_name[30];

	int err;

	struct amdgpu_firmware_info *info = NULL;

	const struct common_firmware_header *header = NULL;
@@ -982,15 +981,15 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) 
	}



	if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {

		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp_2.bin", chip_name);

		err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name);

		err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw,

					   "amdgpu/%s_pfp_2.bin", chip_name);

		if (err == -ENODEV) {

			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);

			err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name);

			err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw,

						   "amdgpu/%s_pfp.bin", chip_name);

		}

	} else {

		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);

		err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name);

		err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw,

					   "amdgpu/%s_pfp.bin", chip_name);

	}

	if (err)

		goto out;
@@ -999,15 +998,15 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) 
	adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);



	if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {

		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me_2.bin", chip_name);

		err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name);

		err = amdgpu_ucode_request(adev, &adev->gfx.me_fw,

					   "amdgpu/%s_me_2.bin", chip_name);

		if (err == -ENODEV) {

			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);

			err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name);

			err = amdgpu_ucode_request(adev, &adev->gfx.me_fw,

						   "amdgpu/%s_me.bin", chip_name);

		}

	} else {

		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);

		err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name);

		err = amdgpu_ucode_request(adev, &adev->gfx.me_fw,

					   "amdgpu/%s_me.bin", chip_name);

	}

	if (err)

		goto out;
@@ -1017,15 +1016,15 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) 
	adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);



	if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {

		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce_2.bin", chip_name);

		err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name);

		err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw,

					   "amdgpu/%s_ce_2.bin", chip_name);

		if (err == -ENODEV) {

			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);

			err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name);

			err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw,

						   "amdgpu/%s_ce.bin", chip_name);

		}

	} else {

		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);

		err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name);

		err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw,

					   "amdgpu/%s_ce.bin", chip_name);

	}

	if (err)

		goto out;
@@ -1044,8 +1043,8 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) 
	} else

		adev->virt.chained_ib_support = false;



	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);

	err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name);

	err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw,

				   "amdgpu/%s_rlc.bin", chip_name);

	if (err)

		goto out;

	rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
@@ -1093,15 +1092,15 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) 
		adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);



	if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {

		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec_2.bin", chip_name);

		err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name);

		err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw,

					   "amdgpu/%s_mec_2.bin", chip_name);

		if (err == -ENODEV) {

			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);

			err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name);

			err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw,

						   "amdgpu/%s_mec.bin", chip_name);

		}

	} else {

		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);

		err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name);

		err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw,

					   "amdgpu/%s_mec.bin", chip_name);

	}

	if (err)

		goto out;
@@ -1112,15 +1111,15 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) 
	if ((adev->asic_type != CHIP_STONEY) &&

	    (adev->asic_type != CHIP_TOPAZ)) {

		if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {

			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2_2.bin", chip_name);

			err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name);

			err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw,

						   "amdgpu/%s_mec2_2.bin", chip_name);

			if (err == -ENODEV) {

				snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);

				err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name);

				err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw,

							   "amdgpu/%s_mec2.bin", chip_name);

			}

		} else {

			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);

			err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name);

			err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw,

						   "amdgpu/%s_mec2.bin", chip_name);

		}

		if (!err) {

			cp_hdr = (const struct gfx_firmware_header_v1_0 *)
@@ -1194,9 +1193,7 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) 


out:

	if (err) {

		dev_err(adev->dev,

			"gfx8: Failed to load firmware \"%s\"\n",

			fw_name);

		dev_err(adev->dev, "gfx8: Failed to load firmware %s gfx firmware\n", chip_name);

		amdgpu_ucode_release(&adev->gfx.pfp_fw);

		amdgpu_ucode_release(&adev->gfx.me_fw);

		amdgpu_ucode_release(&adev->gfx.ce_fw);