Commit 3a568e3a authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'soc-fixes-6.7-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc 

Pull ARM SoC fixes from Arnd Bergmann:
 "A couple of platforms have some last-minute fixes, in particular:

   - riscv gets some fixes for noncoherent DMA on the renesas and thead
     platforms and dts fix for SPI on the visionfive 2 board

   - Qualcomm Snapdragon gets three dts fixes to address board specific
     regressions on the pmic and gpio nodes

   - Rockchip platforms get multiple dts fixes to address issues on the
     recent rk3399 platform as well as the older rk3128 platform that
     apparently regressed a while ago.

   - TI OMAP gets some trivial code and dts fixes and a regression fix
     for the omap1 ams-delta modem

   - NXP i.MX firmware has one fix for a use-after-free but in its error
     handling"

* tag 'soc-fixes-6.7-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (25 commits)
  soc: renesas: ARCH_R9A07G043 depends on !RISCV_ISA_ZICBOM
  riscv: only select DMA_DIRECT_REMAP from RISCV_ISA_ZICBOM and ERRATA_THEAD_PBMT
  riscv: RISCV_NONSTANDARD_CACHE_OPS shouldn't depend on RISCV_DMA_NONCOHERENT
  riscv: dts: thead: set dma-noncoherent to soc bus
  arm64: dts: rockchip: Fix i2s0 pin conflict on ROCK Pi 4 boards
  arm64: dts: rockchip: Add i2s0-2ch-bus-bclk-off pins to RK3399
  clk: ti: Fix missing omap5 mcbsp functional clock and aliases
  clk: ti: Fix missing omap4 mcbsp functional clock and aliases
  ARM: OMAP1: ams-delta: Fix MODEM initialization failure
  soc: renesas: Make ARCH_R9A07G043 depend on required options
  riscv: dts: starfive: visionfive 2: correct spi's ss pin
  firmware/imx-dsp: Fix use_after_free in imx_dsp_setup_channels()
  ARM: OMAP: timer32K: fix all kernel-doc warnings
  ARM: omap2: fix a debug printk
  ARM: dts: rockchip: Fix timer clocks for RK3128
  ARM: dts: rockchip: Add missing quirk for RK3128's dma engine
  ARM: dts: rockchip: Add missing arm timer interrupt for RK3128
  ARM: dts: rockchip: Fix i2c0 register address for RK3128
  arm64: dts: rockchip: set codec system-clock-fixed on px30-ringneck-haikou
  arm64: dts: rockchip: use codec as clock master on px30-ringneck-haikou
  ...
parents c17cda15 736a4aad

MAINTAINERS

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@@ -13846,9 +13846,10 @@ F: Documentation/devicetree/bindings/media/amlogic,gx-vdec.yaml 
F:	drivers/staging/media/meson/vdec/









METHODE UDPU SUPPORT









M:	Vladimir Vid <vladimir.vid@sartura.hr>









M:	Robert Marko <robert.marko@sartura.hr>









S:	Maintained









F:	arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts









F:	arch/arm64/boot/dts/marvell/armada-3720-eDPU.dts









F:	arch/arm64/boot/dts/marvell/armada-3720-uDPU.*

















MHI BUS









M:	Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
































arch/arm/boot/dts/rockchip/rk3128.dtsi



+10
−8






























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@@ -64,7 +64,8 @@ timer {







		compatible = "arm,armv7-timer";









		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,









			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,









			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;









			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,









			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;









		arm,cpu-registers-not-fw-configured;









		clock-frequency = <24000000>;









	};








@@ -233,7 +234,7 @@ timer0: timer@20044000 {







		compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";









		reg = <0x20044000 0x20>;









		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;









		clocks = <&cru PCLK_TIMER>, <&xin24m>;









		clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;









		clock-names = "pclk", "timer";









	};


















@@ -241,7 +242,7 @@ timer1: timer@20044020 {







		compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";









		reg = <0x20044020 0x20>;









		interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;









		clocks = <&cru PCLK_TIMER>, <&xin24m>;









		clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER1>;









		clock-names = "pclk", "timer";









	};


















@@ -249,7 +250,7 @@ timer2: timer@20044040 {







		compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";









		reg = <0x20044040 0x20>;









		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;









		clocks = <&cru PCLK_TIMER>, <&xin24m>;









		clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER2>;









		clock-names = "pclk", "timer";









	};


















@@ -257,7 +258,7 @@ timer3: timer@20044060 {







		compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";









		reg = <0x20044060 0x20>;









		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;









		clocks = <&cru PCLK_TIMER>, <&xin24m>;









		clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER3>;









		clock-names = "pclk", "timer";









	};


















@@ -265,7 +266,7 @@ timer4: timer@20044080 {







		compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";









		reg = <0x20044080 0x20>;









		interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;









		clocks = <&cru PCLK_TIMER>, <&xin24m>;









		clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER4>;









		clock-names = "pclk", "timer";









	};


















@@ -273,7 +274,7 @@ timer5: timer@200440a0 {







		compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";









		reg = <0x200440a0 0x20>;









		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;









		clocks = <&cru PCLK_TIMER>, <&xin24m>;









		clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER5>;









		clock-names = "pclk", "timer";









	};


















@@ -426,7 +427,7 @@ saradc: saradc@2006c000 {

















	i2c0: i2c@20072000 {









		compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";









		reg = <20072000 0x1000>;









		reg = <0x20072000 0x1000>;









		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;









		clock-names = "i2c";









		clocks = <&cru PCLK_I2C0>;








@@ -458,6 +459,7 @@ pdma: dma-controller@20078000 {







		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,









			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;









		arm,pl330-broken-no-flushp;









		arm,pl330-periph-burst;









		clocks = <&cru ACLK_DMAC>;









		clock-names = "apb_pclk";









		#dma-cells = <1>;
































arch/arm/boot/dts/ti/omap/omap4-l4-abe.dtsi



+6
−0






























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@@ -109,6 +109,8 @@ mcbsp1: mcbsp@0 {







				reg = <0x0 0xff>, /* MPU private access */









				      <0x49022000 0xff>; /* L3 Interconnect */









				reg-names = "mpu", "dma";









				clocks = <&abe_clkctrl OMAP4_MCBSP1_CLKCTRL 24>;









				clock-names = "fck";









				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;









				interrupt-names = "common";









				ti,buffer-size = <128>;








@@ -142,6 +144,8 @@ mcbsp2: mcbsp@0 {







				reg = <0x0 0xff>, /* MPU private access */









				      <0x49024000 0xff>; /* L3 Interconnect */









				reg-names = "mpu", "dma";









				clocks = <&abe_clkctrl OMAP4_MCBSP2_CLKCTRL 24>;









				clock-names = "fck";









				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;









				interrupt-names = "common";









				ti,buffer-size = <128>;








@@ -175,6 +179,8 @@ mcbsp3: mcbsp@0 {







				reg = <0x0 0xff>, /* MPU private access */









				      <0x49026000 0xff>; /* L3 Interconnect */









				reg-names = "mpu", "dma";









				clocks = <&abe_clkctrl OMAP4_MCBSP3_CLKCTRL 24>;









				clock-names = "fck";









				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;









				interrupt-names = "common";









				ti,buffer-size = <128>;
































arch/arm/boot/dts/ti/omap/omap4-l4.dtsi



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@@ -2043,6 +2043,8 @@ mcbsp4: mcbsp@0 {







				compatible = "ti,omap4-mcbsp";









				reg = <0x0 0xff>; /* L4 Interconnect */









				reg-names = "mpu";









				clocks = <&l4_per_clkctrl OMAP4_MCBSP4_CLKCTRL 24>;









				clock-names = "fck";









				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;









				interrupt-names = "common";









				ti,buffer-size = <128>;
































arch/arm/boot/dts/ti/omap/omap5-l4-abe.dtsi



+6
−0






























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@@ -109,6 +109,8 @@ mcbsp1: mcbsp@0 {







				reg = <0x0 0xff>, /* MPU private access */









				      <0x49022000 0xff>; /* L3 Interconnect */









				reg-names = "mpu", "dma";









				clocks = <&abe_clkctrl OMAP5_MCBSP1_CLKCTRL 24>;









				clock-names = "fck";









				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;









				interrupt-names = "common";









				ti,buffer-size = <128>;








@@ -142,6 +144,8 @@ mcbsp2: mcbsp@0 {







				reg = <0x0 0xff>, /* MPU private access */









				      <0x49024000 0xff>; /* L3 Interconnect */









				reg-names = "mpu", "dma";









				clocks = <&abe_clkctrl OMAP5_MCBSP2_CLKCTRL 24>;









				clock-names = "fck";









				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;









				interrupt-names = "common";









				ti,buffer-size = <128>;








@@ -175,6 +179,8 @@ mcbsp3: mcbsp@0 {







				reg = <0x0 0xff>, /* MPU private access */









				      <0x49026000 0xff>; /* L3 Interconnect */









				reg-names = "mpu", "dma";









				clocks = <&abe_clkctrl OMAP5_MCBSP3_CLKCTRL 24>;









				clock-names = "fck";









				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;









				interrupt-names = "common";









				ti,buffer-size = <128>;