Commit 3a73e376 authored by Neil Armstrong's avatar Neil Armstrong Committed by Dmitry Baryshkov
Browse files

drm/msm: dsi: add support for DSI-PHY on SM8650 



Add DSI PHY support for the SM8650 platform.

Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/564976/
Link: https://lore.kernel.org/r/20231030-topic-sm8650-upstream-mdss-v2-7-43f1887c82b8@linaro.org


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent e6488c2a

drivers/gpu/drm/msm/dsi/phy/dsi_phy.c

+2 −0
Original line number Diff line number Diff line
@@ -587,6 +587,8 @@ static const struct of_device_id dsi_phy_dt_match[] = { 
	  .data = &dsi_phy_5nm_8450_cfgs },

	{ .compatible = "qcom,sm8550-dsi-phy-4nm",

	  .data = &dsi_phy_4nm_8550_cfgs },

	{ .compatible = "qcom,sm8650-dsi-phy-4nm",

	  .data = &dsi_phy_4nm_8650_cfgs },

#endif

	{}

};

drivers/gpu/drm/msm/dsi/phy/dsi_phy.h

+1 −0
Original line number Diff line number Diff line
@@ -62,6 +62,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs; 
extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs;

extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs;

extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs;

extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs;



struct msm_dsi_dphy_timing {

	u32 clk_zero;

drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c

+27 −0
Original line number Diff line number Diff line
@@ -1121,6 +1121,10 @@ static const struct regulator_bulk_data dsi_phy_7nm_37750uA_regulators[] = { 
	{ .supply = "vdds", .init_load_uA = 37550 },

};



static const struct regulator_bulk_data dsi_phy_7nm_98000uA_regulators[] = {

	{ .supply = "vdds", .init_load_uA = 98000 },

};



static const struct regulator_bulk_data dsi_phy_7nm_97800uA_regulators[] = {

	{ .supply = "vdds", .init_load_uA = 97800 },

};
@@ -1281,3 +1285,26 @@ const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs = { 
	.num_dsi_phy = 2,

	.quirks = DSI_PHY_7NM_QUIRK_V5_2,

};



const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs = {

	.has_phy_lane = true,

	.regulator_data = dsi_phy_7nm_98000uA_regulators,

	.num_regulators = ARRAY_SIZE(dsi_phy_7nm_98000uA_regulators),

	.ops = {

		.enable = dsi_7nm_phy_enable,

		.disable = dsi_7nm_phy_disable,

		.pll_init = dsi_pll_7nm_init,

		.save_pll_state = dsi_7nm_pll_save_state,

		.restore_pll_state = dsi_7nm_pll_restore_state,

		.set_continuous_clock = dsi_7nm_set_continuous_clock,

	},

	.min_pll_rate = 600000000UL,

#ifdef CONFIG_64BIT

	.max_pll_rate = 5000000000UL,

#else

	.max_pll_rate = ULONG_MAX,

#endif

	.io_start = { 0xae95000, 0xae97000 },

	.num_dsi_phy = 2,

	.quirks = DSI_PHY_7NM_QUIRK_V5_2,

};