Commit 3a9cf301 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/dp: Add POST_LT_ADJ_REQ helpers 



Add small helpers (drm_dp_post_lt_adj_req_supported() and
drm_dp_post_lt_adj_req_in_progress()) to help with implementing
the POST_LT_ADJ_REQ sequence.

Tested-by: default avatarImre Deak <imre.deak@intel.com>
Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250718120154.15492-3-ville.syrjala@linux.intel.com
parent 2b8e4b94

drivers/gpu/drm/display/drm_dp_helper.c

+8 −0
Original line number Diff line number Diff line
@@ -123,6 +123,14 @@ bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 
}

EXPORT_SYMBOL(drm_dp_clock_recovery_ok);



bool drm_dp_post_lt_adj_req_in_progress(const u8 link_status[DP_LINK_STATUS_SIZE])

{

	u8 lane_align = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED);



	return lane_align & DP_POST_LT_ADJ_REQ_IN_PROGRESS;

}

EXPORT_SYMBOL(drm_dp_post_lt_adj_req_in_progress);



u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],

				     int lane)

{

include/drm/display/drm_dp_helper.h

+8 −0
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@ bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 
			  int lane_count);

bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],

			      int lane_count);

bool drm_dp_post_lt_adj_req_in_progress(const u8 link_status[DP_LINK_STATUS_SIZE]);

u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],

				     int lane);

u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
@@ -155,6 +156,13 @@ drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 
		(dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP);

}



static inline bool

drm_dp_post_lt_adj_req_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])

{

	return dpcd[DP_DPCD_REV] >= 0x13 &&

		(dpcd[DP_MAX_LANE_COUNT] & DP_POST_LT_ADJ_REQ_SUPPORTED);

}



static inline bool

drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])

{