Commit 3ac022bf authored by Chunyan Zhang's avatar Chunyan Zhang Committed by Paul Walmsley
Browse files

raid6: test: Add support for RISC-V 



Add RISC-V code to be compiled to allow the userspace raid6test program
to be built and run on RISC-V.

Signed-off-by: default avatarChunyan Zhang <zhang.lyra@gmail.com>
Reviewed-by: default avatarAlexandre Ghiti <alexghiti@rivosinc.com>
Tested-by: default avatarAlexandre Ghiti <alexghiti@rivosinc.com>
Link: https://patch.msgid.link/20250718072711.3865118-6-zhangchunyan@iscas.ac.cn


Signed-off-by: default avatarPaul Walmsley <pjw@kernel.org>
parent 3c58d7a5

lib/raid6/test/Makefile

+8 −0
Original line number Diff line number Diff line
@@ -35,6 +35,11 @@ ifeq ($(ARCH),aarch64) 
        HAS_NEON = yes

endif



ifeq ($(findstring riscv,$(ARCH)),riscv)

        CFLAGS += -I../../../arch/riscv/include -DCONFIG_RISCV=1

        HAS_RVV = yes

endif



ifeq ($(findstring ppc,$(ARCH)),ppc)

        CFLAGS += -I../../../arch/powerpc/include

        HAS_ALTIVEC := $(shell printf '$(pound)include <altivec.h>\nvector int a;\n' |\
@@ -63,6 +68,9 @@ else ifeq ($(HAS_ALTIVEC),yes) 
                vpermxor1.o vpermxor2.o vpermxor4.o vpermxor8.o

else ifeq ($(ARCH),loongarch64)

        OBJS += loongarch_simd.o recov_loongarch_simd.o

else ifeq ($(HAS_RVV),yes)

        OBJS   += rvv.o recov_rvv.o

        CFLAGS += -DCONFIG_RISCV_ISA_V=1

endif



.c.o: