Commit 3ac5e840 authored by Bjorn Andersson's avatar Bjorn Andersson
Browse files

Merge branch 'arm64-fixes-for-6.11' into HEAD 

Merge the X1E PCIe fixes from the fixes branch, to avoid merge conflicts
with the addition of PCIe5 and the modem.
parents dfd06c0e 86c71c0e

arch/arm64/boot/dts/qcom/ipq5332.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -320,8 +320,8 @@ usb: usb@8af8800 { 
			reg = <0x08af8800 0x400>;



			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 53 IRQ_TYPE_EDGE_BOTH>,

				     <GIC_SPI 52 IRQ_TYPE_EDGE_BOTH>;

				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "pwr_event",

					  "dp_hs_phy_irq",

					  "dm_hs_phy_irq";

arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts

+39 −3
Original line number Diff line number Diff line
@@ -278,6 +278,13 @@ regulators-6 { 
		vdd-l3-supply = <&vreg_s1f_0p7>;

		vdd-s1-supply = <&vph_pwr>;

		vdd-s2-supply = <&vph_pwr>;



		vreg_l3i_0p8: ldo3 {

			regulator-name = "vreg_l3i_0p8";

			regulator-min-microvolt = <880000>;

			regulator-max-microvolt = <920000>;

			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;

		};

	};



	regulators-7 {
@@ -423,11 +430,17 @@ &mdss_dp3_phy { 
};



&pcie4 {

	perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;

	wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;



	pinctrl-0 = <&pcie4_default>;

	pinctrl-names = "default";



	status = "okay";

};



&pcie4_phy {

	vdda-phy-supply = <&vreg_l3j_0p8>;

	vdda-phy-supply = <&vreg_l3i_0p8>;

	vdda-pll-supply = <&vreg_l3e_1p2>;



	status = "okay";
@@ -513,7 +526,30 @@ nvme_reg_en: nvme-reg-en-state { 
		bias-disable;

	};



	pcie6a_default: pcie2a-default-state {

	pcie4_default: pcie4-default-state {

		clkreq-n-pins {

			pins = "gpio147";

			function = "pcie4_clk";

			drive-strength = <2>;

			bias-pull-up;

		};



		perst-n-pins {

			pins = "gpio146";

			function = "gpio";

			drive-strength = <2>;

			bias-disable;

		};



		wake-n-pins {

			pins = "gpio148";

			function = "gpio";

			drive-strength = <2>;

			bias-pull-up;

		};

	};



	pcie6a_default: pcie6a-default-state {

		clkreq-n-pins {

			pins = "gpio153";

			function = "pcie6a_clk";
@@ -525,7 +561,7 @@ perst-n-pins { 
			pins = "gpio152";

			function = "gpio";

			drive-strength = <2>;

			bias-pull-down;

			bias-disable;

		};



		wake-n-pins {

arch/arm64/boot/dts/qcom/x1e80100-crd.dts

+37 −8
Original line number Diff line number Diff line
@@ -773,11 +773,17 @@ &mdss_dp3_phy { 
};



&pcie4 {

	perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;

	wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;



	pinctrl-0 = <&pcie4_default>;

	pinctrl-names = "default";



	status = "okay";

};



&pcie4_phy {

	vdda-phy-supply = <&vreg_l3j_0p8>;

	vdda-phy-supply = <&vreg_l3i_0p8>;

	vdda-pll-supply = <&vreg_l3e_1p2>;



	status = "okay";
@@ -958,7 +964,30 @@ nvme_reg_en: nvme-reg-en-state { 
		bias-disable;

	};



	pcie6a_default: pcie2a-default-state {

	pcie4_default: pcie4-default-state {

		clkreq-n-pins {

			pins = "gpio147";

			function = "pcie4_clk";

			drive-strength = <2>;

			bias-pull-up;

		};



		perst-n-pins {

			pins = "gpio146";

			function = "gpio";

			drive-strength = <2>;

			bias-disable;

		};



		wake-n-pins {

			pins = "gpio148";

			function = "gpio";

			drive-strength = <2>;

			bias-pull-up;

		};

	};



	pcie6a_default: pcie6a-default-state {

		clkreq-n-pins {

			pins = "gpio153";

			function = "pcie6a_clk";
@@ -970,7 +999,7 @@ perst-n-pins { 
			pins = "gpio152";

			function = "gpio";

			drive-strength = <2>;

			bias-pull-down;

			bias-disable;

		};



		wake-n-pins {

arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts

+46 −8
Original line number Diff line number Diff line
@@ -625,16 +625,31 @@ &mdss_dp3_phy { 
};



&pcie4 {

	perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;

	wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;



	pinctrl-0 = <&pcie4_default>;

	pinctrl-names = "default";



	status = "okay";

};



&pcie4_phy {

	vdda-phy-supply = <&vreg_l3j_0p8>;

	vdda-phy-supply = <&vreg_l3i_0p8>;

	vdda-pll-supply = <&vreg_l3e_1p2>;



	status = "okay";

};



&pcie4_port0 {

	wifi@0 {

		compatible = "pci17cb,1107";

		reg = <0x10000 0x0 0x0 0x0 0x0>;



		qcom,ath12k-calibration-variant = "LES790";

	};

};



&pcie6a {

	perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;

	wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
@@ -786,7 +801,30 @@ nvme_reg_en: nvme-reg-en-state { 
		bias-disable;

	};



	pcie6a_default: pcie2a-default-state {

	pcie4_default: pcie4-default-state {

		clkreq-n-pins {

			pins = "gpio147";

			function = "pcie4_clk";

			drive-strength = <2>;

			bias-pull-up;

		};



		perst-n-pins {

			pins = "gpio146";

			function = "gpio";

			drive-strength = <2>;

			bias-disable;

		};



		wake-n-pins {

			pins = "gpio148";

			function = "gpio";

			drive-strength = <2>;

			bias-pull-up;

		};

	};



	pcie6a_default: pcie6a-default-state {

		clkreq-n-pins {

			pins = "gpio153";

			function = "pcie6a_clk";
@@ -798,7 +836,7 @@ perst-n-pins { 
			pins = "gpio152";

			function = "gpio";

			drive-strength = <2>;

			bias-pull-down;

			bias-disable;

		};



		wake-n-pins {

arch/arm64/boot/dts/qcom/x1e80100-qcp.dts

+37 −8
Original line number Diff line number Diff line
@@ -660,11 +660,17 @@ &mdss_dp3_phy { 
};



&pcie4 {

	perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;

	wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;



	pinctrl-0 = <&pcie4_default>;

	pinctrl-names = "default";



	status = "okay";

};



&pcie4_phy {

	vdda-phy-supply = <&vreg_l3j_0p8>;

	vdda-phy-supply = <&vreg_l3i_0p8>;

	vdda-pll-supply = <&vreg_l3e_1p2>;



	status = "okay";
@@ -808,7 +814,30 @@ nvme_reg_en: nvme-reg-en-state { 
		bias-disable;

	};



	pcie6a_default: pcie2a-default-state {

	pcie4_default: pcie4-default-state {

		clkreq-n-pins {

			pins = "gpio147";

			function = "pcie4_clk";

			drive-strength = <2>;

			bias-pull-up;

		};



		perst-n-pins {

			pins = "gpio146";

			function = "gpio";

			drive-strength = <2>;

			bias-disable;

		};



		wake-n-pins {

			pins = "gpio148";

			function = "gpio";

			drive-strength = <2>;

			bias-pull-up;

		};

	};



	pcie6a_default: pcie6a-default-state {

		clkreq-n-pins {

			pins = "gpio153";

			function = "pcie6a_clk";
@@ -820,7 +849,7 @@ perst-n-pins { 
			pins = "gpio152";

			function = "gpio";

			drive-strength = <2>;

			bias-pull-down;

			bias-disable;

		};



		wake-n-pins {