Merge tag 'xilinx-defconfig-for-6.20' of https://github.com/Xilinx/linux-xlnx into soc/defconfig

CONFIG_PCIE_RENESAS_RZG3S_HOST=y

CONFIG_PCIE_ROCKCHIP_HOST=m

CONFIG_PCI_XGENE=y

CONFIG_PCIE_XILINX=y

CONFIG_PCIE_XILINX_DMA_PL=y

CONFIG_PCIE_XILINX_NWL=y

CONFIG_PCIE_XILINX_CPM=y

CONFIG_PCI_IMX6_HOST=y

CONFIG_PCI_LAYERSCAPE=y

CONFIG_PCI_HISI=y

CONFIG_QCOM_QSEECOM_UEFISECAPP=y

CONFIG_EXYNOS_ACPM_PROTOCOL=m

CONFIG_TEGRA_BPMP=y

CONFIG_ZYNQMP_FIRMWARE_DEBUG=y

CONFIG_GNSS=m

CONFIG_GNSS_MTK_SERIAL=m

CONFIG_MTD=y

CONFIG_QCOM_FASTRPC=m

CONFIG_SRAM=y

CONFIG_PCI_ENDPOINT_TEST=m

CONFIG_XILINX_SDFEC=m

CONFIG_EEPROM_AT24=m

CONFIG_EEPROM_AT25=m

CONFIG_UACCE=m

CONFIG_DWMAC_TEGRA=m

CONFIG_TI_K3_AM65_CPSW_NUSS=y

CONFIG_TI_ICSSG_PRUETH=m

CONFIG_XILINX_AXI_EMAC=m

CONFIG_QCOM_IPA=m

CONFIG_MESON_GXL_PHY=m

CONFIG_AQUANTIA_PHY=y

CONFIG_DP83869_PHY=m

CONFIG_DP83TD510_PHY=y

CONFIG_VITESSE_PHY=y

CONFIG_XILINX_GMII2RGMII=m

CONFIG_CAN_FLEXCAN=m

CONFIG_CAN_XILINXCAN=m

CONFIG_CAN_M_CAN=m

CONFIG_CAN_M_CAN_PLATFORM=m

CONFIG_CAN_RCAR=m

CONFIG_I2C_SH_MOBILE=y

CONFIG_I2C_TEGRA=y

CONFIG_I2C_UNIPHIER_F=y

CONFIG_I2C_XILINX=m

CONFIG_I2C_RCAR=y

CONFIG_I2C_CROS_EC_TUNNEL=y

CONFIG_SPI=y

CONFIG_SPI_SUN6I=y

CONFIG_SPI_TEGRA210_QUAD=m

CONFIG_SPI_TEGRA114=m

CONFIG_SPI_XILINX=m

CONFIG_SPI_ZYNQMP_GQSPI=m

CONFIG_SPI_SPIDEV=m

CONFIG_SPMI=y

CONFIG_SPMI_APPLE=m

CONFIG_GPIO_VF610=y

CONFIG_GPIO_XGENE=y

CONFIG_GPIO_XGENE_SB=y

CONFIG_GPIO_XILINX=m

CONFIG_GPIO_ZYNQ=m

CONFIG_GPIO_MAX732X=y

CONFIG_GPIO_PCA953X=y

CONFIG_GPIO_PCA953X_IRQ=y

CONFIG_UNIPHIER_THERMAL=y

CONFIG_KHADAS_MCU_FAN_THERMAL=m

CONFIG_WATCHDOG=y

CONFIG_XILINX_WATCHDOG=m

CONFIG_XILINX_WINDOW_WATCHDOG=m

CONFIG_SL28CPLD_WATCHDOG=m

CONFIG_ARM_SP805_WATCHDOG=y

CONFIG_ARM_SBSA_WATCHDOG=y

CONFIG_DRM_PANFROST=m

CONFIG_DRM_PANTHOR=m

CONFIG_DRM_TIDSS=m

CONFIG_DRM_ZYNQMP_DPSUB=m

CONFIG_DRM_ZYNQMP_DPSUB_AUDIO=y

CONFIG_DRM_POWERVR=m

CONFIG_FB=y

CONFIG_FB_EFI=y

CONFIG_SND_SOC_TEGRA_AUDIO_GRAPH_CARD=m

CONFIG_SND_SOC_DAVINCI_MCASP=m

CONFIG_SND_SOC_J721E_EVM=m

CONFIG_SND_SOC_XILINX_I2S=m

CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER=m

CONFIG_SND_SOC_XILINX_SPDIF=m

CONFIG_SND_SOC_AK4613=m

CONFIG_SND_SOC_AK4619=m

CONFIG_SND_SOC_DA7213=m

CONFIG_USB_QCOM_EUD=m

CONFIG_USB_HSIC_USB3503=y

CONFIG_USB_ONBOARD_DEV=m

CONFIG_USB_ONBOARD_DEV_USB5744=y

CONFIG_NOP_USB_XCEIV=y

CONFIG_USB_MXS_PHY=m

CONFIG_USB_GADGET=y

CONFIG_EDAC=y

CONFIG_EDAC_GHES=y

CONFIG_EDAC_LAYERSCAPE=m

CONFIG_EDAC_ZYNQMP=m

CONFIG_EDAC_VERSAL=m

CONFIG_RTC_CLASS=y

CONFIG_RTC_DRV_DS1307=m

CONFIG_RTC_DRV_HYM8563=m

CONFIG_RTC_DRV_PCF2127=m

CONFIG_RTC_DRV_DA9063=m

CONFIG_RTC_DRV_EFI=y

CONFIG_RTC_DRV_ZYNQMP=m

CONFIG_RTC_DRV_CROS_EC=y

CONFIG_RTC_DRV_FSL_FTM_ALARM=m

CONFIG_RTC_DRV_S3C=y

CONFIG_TEGRA186_GPC_DMA=y

CONFIG_TEGRA20_APB_DMA=y

CONFIG_TEGRA210_ADMA=m

CONFIG_XILINX_DMA=m

CONFIG_XILINX_ZYNQMP_DMA=m

CONFIG_XILINX_ZYNQMP_DPDMA=m

CONFIG_MTK_UART_APDMA=m

CONFIG_QCOM_BAM_DMA=y

CONFIG_QCOM_GPI_DMA=m

CONFIG_CLK_RENESAS_VBATTB=m

CONFIG_EXYNOS_ACPM_CLK=m

CONFIG_CLK_SOPHGO_CV1800=y

CONFIG_XILINX_VCU=m

CONFIG_COMMON_CLK_XLNX_CLKWZRD=m

CONFIG_HWSPINLOCK=y

CONFIG_HWSPINLOCK_OMAP=m

CONFIG_HWSPINLOCK_QCOM=y

CONFIG_SOPHGO_CV1800B_ADC=m

CONFIG_TI_ADS1015=m

CONFIG_TI_AM335X_ADC=m

CONFIG_XILINX_XADC=m

CONFIG_XILINX_AMS=m

CONFIG_IIO_CROS_EC_SENSORS_CORE=m

CONFIG_IIO_CROS_EC_SENSORS=m

CONFIG_IIO_ST_LSM6DSX=m

CONFIG_PWM_TIECAP=m

CONFIG_PWM_TIEHRPWM=m

CONFIG_PWM_VISCONTI=m

CONFIG_PWM_XILINX=m

CONFIG_SL28CPLD_INTC=y

CONFIG_XILINX_INTC=y

CONFIG_QCOM_PDC=y

CONFIG_QCOM_MPM=y

CONFIG_TI_SCI_INTR_IRQCHIP=y

CONFIG_PHY_TEGRA_XUSB=y

CONFIG_PHY_AM654_SERDES=m

CONFIG_PHY_J721E_WIZ=m

CONFIG_PHY_XILINX_ZYNQMP=m

CONFIG_ARM_CCI_PMU=m

CONFIG_ARM_CCN=m

CONFIG_ARM_CMN=m

CONFIG_NVMEM_SPMI_SDAM=m

CONFIG_NVMEM_SUNXI_SID=y

CONFIG_NVMEM_UNIPHIER_EFUSE=y

CONFIG_NVMEM_ZYNQMP=m

CONFIG_FPGA=y

CONFIG_FPGA_MGR_ALTERA_CVP=m

CONFIG_FPGA_MGR_STRATIX10_SOC=m

CONFIG_FPGA_BRIDGE=m

CONFIG_ALTERA_FREEZE_BRIDGE=m

CONFIG_XILINX_PR_DECOUPLER=m

CONFIG_FPGA_REGION=m

CONFIG_OF_FPGA_REGION=m

CONFIG_OF_OVERLAY=y

CONFIG_FPGA_MGR_ZYNQMP_FPGA=m

CONFIG_FPGA_MGR_VERSAL_FPGA=m

CONFIG_TEE=y

CONFIG_OPTEE=y

CONFIG_MUX_GPIO=m

CONFIG_CRYPTO_DEV_QCE=m

CONFIG_CRYPTO_DEV_QCOM_RNG=m

CONFIG_CRYPTO_DEV_TEGRA=m

CONFIG_CRYPTO_DEV_XILINX_TRNG=m

CONFIG_CRYPTO_DEV_ZYNQMP_AES=m

CONFIG_CRYPTO_DEV_ZYNQMP_SHA3=m

CONFIG_CRYPTO_DEV_CCREE=m

CONFIG_CRYPTO_DEV_HISI_SEC2=m

CONFIG_CRYPTO_DEV_HISI_ZIP=m