Commit 3b0cf6ab authored by John Madieu's avatar John Madieu Committed by Geert Uytterhoeven
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pinctrl: renesas: rzg2l: Refactor OEN register PWPR handling 



Extract the OEN register write with PWPR protection logic into a helper
function to eliminate code duplication between rzg2l_write_oen() and
rzg2l_pinctrl_resume_noirq().

Introduce rzg2l_oen_write_with_pwpr() helper that encapsulates the
PWPR unlock, OEN register write, and PWPR lock sequence. This helper
must be called with pctrl->lock already held by the caller.

Reported-by: default avatarPavel Machek <pavel@denx.de>
Closes: https://lore.kernel.org/cip-dev/OS9PR01MB16368C765305362F5F4132759FFC4A@OS9PR01MB16368.jpnprd01.prod.outlook.com/T/#u


Signed-off-by: default avatarJohn Madieu <john.madieu.xa@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251106080758.36645-1-john.madieu.xa@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 8903597d

drivers/pinctrl/renesas/pinctrl-rzg2l.c

+33 −20
Original line number Diff line number Diff line
@@ -1112,13 +1112,37 @@ static int rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin) 
	return !(readb(pctrl->base + pctrl->data->hwcfg->regs.oen) & BIT(bit));

}



static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)

/**

 * rzg2l_oen_write_with_pwpr - Write to OEN register with PWPR protection

 * @pctrl: pinctrl driver data

 * @val: value to write to OEN register

 *

 * Writes to the OEN register, handling PWPR write protection if required

 * by the hardware configuration. Must be called with pctrl->lock held.

 */

static void rzg2l_oen_write_with_pwpr(struct rzg2l_pinctrl *pctrl, u8 val)

{

	const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs;

	u16 oen_offset = pctrl->data->hwcfg->regs.oen;

	u8 pwpr;



	if (pctrl->data->hwcfg->oen_pwpr_lock) {

		pwpr = readb(pctrl->base + regs->pwpr);

		writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr);

	}



	writeb(val, pctrl->base + oen_offset);



	if (pctrl->data->hwcfg->oen_pwpr_lock)

		writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr);

}



static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)

{

	u16 oen_offset = pctrl->data->hwcfg->regs.oen;

	unsigned long flags;

	u8 val, pwpr;

	int bit;

	u8 val;



	if (!pctrl->data->pin_to_oen_bit)

		return -EOPNOTSUPP;
@@ -1133,13 +1157,8 @@ static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oe 
		val &= ~BIT(bit);

	else

		val |= BIT(bit);

	if (pctrl->data->hwcfg->oen_pwpr_lock) {

		pwpr = readb(pctrl->base + regs->pwpr);

		writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr);

	}

	writeb(val, pctrl->base + oen_offset);

	if (pctrl->data->hwcfg->oen_pwpr_lock)

		writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr);



	rzg2l_oen_write_with_pwpr(pctrl, val);

	raw_spin_unlock_irqrestore(&pctrl->lock, flags);



	return 0;
@@ -3200,7 +3219,6 @@ static int rzg2l_pinctrl_resume_noirq(struct device *dev) 
	const struct rzg2l_register_offsets *regs = &hwcfg->regs;

	struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache;

	unsigned long flags;

	u8 pwpr;

	int ret;



	if (!atomic_read(&pctrl->wakeup_path)) {
@@ -3210,16 +3228,11 @@ static int rzg2l_pinctrl_resume_noirq(struct device *dev) 
	}



	writeb(cache->qspi, pctrl->base + QSPI);

	if (pctrl->data->hwcfg->oen_pwpr_lock) {



	raw_spin_lock_irqsave(&pctrl->lock, flags);

		pwpr = readb(pctrl->base + regs->pwpr);

		writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr);

	}

	writeb(cache->oen, pctrl->base + pctrl->data->hwcfg->regs.oen);

	if (pctrl->data->hwcfg->oen_pwpr_lock) {

		writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr);

	rzg2l_oen_write_with_pwpr(pctrl, cache->oen);

	raw_spin_unlock_irqrestore(&pctrl->lock, flags);

	}



	for (u8 i = 0; i < 2; i++) {

		if (regs->sd_ch)

			writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i));