Commit 3b1d5deb authored by Frank Li's avatar Frank Li Committed by Shawn Guo
Browse files

arm64: dts: imx95: add pcie[0,1] and pcie-ep[0,1] support 



Add pcie[0,1] and pcie-ep[0,1] support.

Signed-off-by: default avatarFrank Li <Frank.Li@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent d9c34491

arch/arm64/boot/dts/freescale/imx95.dtsi

+134 −0
Original line number Diff line number Diff line
@@ -1054,5 +1054,139 @@ smmu: iommu@490d0000 { 
				status = "disabled";

			};

		};



		pcie0: pcie@4c300000 {

			compatible = "fsl,imx95-pcie";

			reg = <0 0x4c300000 0 0x10000>,

			      <0 0x60100000 0 0xfe00000>,

			      <0 0x4c360000 0 0x10000>,

			      <0 0x4c340000 0 0x2000>;

			reg-names = "dbi", "config", "atu", "app";

			ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>,

				 <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x10000000>;

			#address-cells = <3>;

			#size-cells = <2>;

			device_type = "pci";

			linux,pci-domain = <0>;

			bus-range = <0x00 0xff>;

			num-lanes = <1>;

			num-viewport = <8>;

			interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "msi";

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 0x7>;

			interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,

					<0 0 0 2 &gic 0 0 GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,

					<0 0 0 3 &gic 0 0 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,

					<0 0 0 4 &gic 0 0 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&scmi_clk IMX95_CLK_HSIO>,

				 <&scmi_clk IMX95_CLK_HSIOPLL>,

				 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,

				 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;

			clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";

			assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,

					 <&scmi_clk IMX95_CLK_HSIOPLL>,

					 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;

			assigned-clock-rates = <3600000000>, <100000000>, <10000000>;

			assigned-clock-parents = <0>, <0>,

						 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;

			power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;

			fsl,max-link-speed = <3>;

			status = "disabled";

		};



		pcie0_ep: pcie-ep@4c300000 {

			compatible = "fsl,imx95-pcie-ep";

			reg = <0 0x4c300000 0 0x10000>,

			      <0 0x4c360000 0 0x1000>,

			      <0 0x4c320000 0 0x1000>,

			      <0 0x4c340000 0 0x2000>,

			      <0 0x4c370000 0 0x10000>,

			      <0x9 0 1 0>;

			reg-names = "dbi","atu", "dbi2", "app", "dma", "addr_space";

			num-lanes = <1>;

			interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "dma";

			clocks = <&scmi_clk IMX95_CLK_HSIO>,

				 <&scmi_clk IMX95_CLK_HSIOPLL>,

				 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,

				 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;

			clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";

			assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,

					 <&scmi_clk IMX95_CLK_HSIOPLL>,

					 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;

			assigned-clock-rates = <3600000000>, <100000000>, <10000000>;

			assigned-clock-parents = <0>, <0>,

						 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;

			power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;

			status = "disabled";

		};



		pcie1: pcie@4c380000 {

			compatible = "fsl,imx95-pcie";

			reg = <0 0x4c380000 0 0x10000>,

			      <8 0x80100000 0 0xfe00000>,

			      <0 0x4c3e0000 0 0x10000>,

			      <0 0x4c3c0000 0 0x2000>;

			reg-names = "dbi", "config", "atu", "app";

			ranges = <0x81000000 0 0x00000000 0x8 0x8ff00000 0 0x00100000>,

				 <0x82000000 0 0x10000000 0xa 0x10000000 0 0x10000000>;

			#address-cells = <3>;

			#size-cells = <2>;

			device_type = "pci";

			linux,pci-domain = <1>;

			bus-range = <0x00 0xff>;

			num-lanes = <1>;

			num-viewport = <8>;

			interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "msi";

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 0x7>;

			interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,

					<0 0 0 2 &gic 0 0 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,

					<0 0 0 3 &gic 0 0 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,

					<0 0 0 4 &gic 0 0 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&scmi_clk IMX95_CLK_HSIO>,

				 <&scmi_clk IMX95_CLK_HSIOPLL>,

				 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,

				 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;

			clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";

			assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,

					 <&scmi_clk IMX95_CLK_HSIOPLL>,

					 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;

			assigned-clock-rates = <3600000000>, <100000000>, <10000000>;

			assigned-clock-parents = <0>, <0>,

						 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;

			power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;

			fsl,max-link-speed = <3>;

			status = "disabled";

		};



		pcie1_ep: pcie-ep@4c380000 {

			compatible = "fsl,imx95-pcie-ep";

			reg = <0 0x4c380000 0 0x10000>,

			      <0 0x4c3e0000 0 0x1000>,

			      <0 0x4c3a0000 0 0x1000>,

			      <0 0x4c3c0000 0 0x2000>,

			      <0 0x4c3f0000 0 0x10000>,

			      <0xa 0 1 0>;

			reg-names = "dbi", "atu", "dbi2", "app", "dma", "addr_space";

			num-lanes = <1>;

			interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "dma";

			clocks = <&scmi_clk IMX95_CLK_HSIO>,

				 <&scmi_clk IMX95_CLK_HSIOPLL>,

				 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,

				 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;

			clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";

			assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,

					 <&scmi_clk IMX95_CLK_HSIOPLL>,

					 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;

			assigned-clock-rates = <3600000000>, <100000000>, <10000000>;

			assigned-clock-parents = <0>, <0>,

						 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;

			power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;

			status = "disabled";

		};

	};

};