Commit 3b2cd606 authored by Biju Das's avatar Biju Das Committed by Greg Kroah-Hartman
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serial: sh-sci: Add support for RZ/G2L SoC



Add serial support for RZ/G2L SoC with earlycon and
extended mode register support.

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210603221758.10305-11-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent d157fca7
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+11 −1
Original line number Diff line number Diff line
@@ -289,7 +289,7 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
	},

	/*
	 * The "SCIFA" that is in RZ/T and RZ/A2.
	 * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T.
	 * It looks like a normal SCIF with FIFO data, but with a
	 * compressed address space. Also, the break out of interrupts
	 * are different: ERI/BRI, RXI, TXI, TEI, DRI.
@@ -306,6 +306,7 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
			[SCFDR]		= { 0x0E, 16 },
			[SCSPTR]	= { 0x10, 16 },
			[SCLSR]		= { 0x12, 16 },
			[SEMR]		= { 0x14, 8 },
		},
		.fifosize = 16,
		.overrun_reg = SCLSR,
@@ -2514,6 +2515,9 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
	if (termios->c_cflag & PARENB)
		bits++;

	if (sci_getreg(port, SEMR)->size)
		serial_port_out(port, SEMR, 0);

	if (best_clk >= 0) {
		if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
			switch (srr + 1) {
@@ -3170,6 +3174,10 @@ static const struct of_device_id of_sci_match[] = {
		.compatible = "renesas,scif-r7s9210",
		.data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
	},
	{
		.compatible = "renesas,scif-r9a07g044",
		.data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
	},
	/* Family-specific types */
	{
		.compatible = "renesas,rcar-gen1-scif",
@@ -3452,6 +3460,7 @@ static int __init rzscifa_early_console_setup(struct earlycon_device *device,
	port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE;
	return early_console_setup(device, PORT_SCIF);
}

static int __init scifa_early_console_setup(struct earlycon_device *device,
					  const char *opt)
{
@@ -3471,6 +3480,7 @@ static int __init hscif_early_console_setup(struct earlycon_device *device,
OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup);
OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
+1 −0
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ enum {
	SCCKS,				/* BRG Clock Select Register */
	HSRTRGR,			/* Rx FIFO Data Count Trigger Register */
	HSTTRGR,			/* Tx FIFO Data Count Trigger Register */
	SEMR,				/* Serial extended mode register */

	SCIx_NR_REGS,
};