Commit 3b450831 authored by Pierre Gondois's avatar Pierre Gondois Committed by Shawn Guo
Browse files

arm64: dts: Update cache properties for freescale 



The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).

Update the Device Trees accordingly.

Signed-off-by: default avatarPierre Gondois <pierre.gondois@arm.com>
Reviewed-by: default avatarChester Lin <clin@suse.com>
Acked-by: default avatarLi Yang <leoyang.li@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 77a1a182

arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -46,6 +46,7 @@ cpu1: cpu@1 { 


		l2: l2-cache {

			compatible = "cache";

			cache-level = <2>;

		};

	};

arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -84,6 +84,7 @@ cpu3: cpu@3 { 


		l2: l2-cache {

			compatible = "cache";

			cache-level = <2>;

		};

	};

arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -79,6 +79,7 @@ cpu3: cpu@3 { 


		l2: l2-cache {

			compatible = "cache";

			cache-level = <2>;

		};

	};

arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -95,18 +95,22 @@ cpu7: cpu@301 { 


	cluster0_l2: l2-cache0 {

		compatible = "cache";

		cache-level = <2>;

	};



	cluster1_l2: l2-cache1 {

		compatible = "cache";

		cache-level = <2>;

	};



	cluster2_l2: l2-cache2 {

		compatible = "cache";

		cache-level = <2>;

	};



	cluster3_l2: l2-cache3 {

		compatible = "cache";

		cache-level = <2>;

	};



	CPU_PW20: cpu-pw20 {

arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -95,18 +95,22 @@ cpu7: cpu@301 { 


	cluster0_l2: l2-cache0 {

		compatible = "cache";

		cache-level = <2>;

	};



	cluster1_l2: l2-cache1 {

		compatible = "cache";

		cache-level = <2>;

	};



	cluster2_l2: l2-cache2 {

		compatible = "cache";

		cache-level = <2>;

	};



	cluster3_l2: l2-cache3 {

		compatible = "cache";

		cache-level = <2>;

	};



	CPU_PW20: cpu-pw20 {