Commit 3b521bf8 authored by Laurentiu Mihalcea's avatar Laurentiu Mihalcea Committed by Abel Vesa
Browse files

dt-bindings: clock: document 8ULP's SIM LPAV 



Add documentation for i.MX8ULP's SIM LPAV module.

Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: default avatarDaniel Baluta <daniel.baluta@nxp.com>
Signed-off-by: default avatarLaurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Link: https://lore.kernel.org/r/20251104120301.913-3-laurentiumihalcea111@gmail.com


Signed-off-by: default avatarAbel Vesa <abel.vesa@linaro.org>
parent 9d97a2fe

Documentation/devicetree/bindings/clock/fsl,imx8ulp-sim-lpav.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/fsl,imx8ulp-sim-lpav.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: NXP i.MX8ULP LPAV System Integration Module (SIM)



maintainers:

  - Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>



description:

  The i.MX8ULP LPAV subsystem contains a block control module known as

  SIM LPAV, which offers functionalities such as clock gating or reset

  line assertion/de-assertion.



properties:

  compatible:

    const: fsl,imx8ulp-sim-lpav



  reg:

    maxItems: 1



  clocks:

    maxItems: 3



  clock-names:

    items:

      - const: bus

      - const: core

      - const: plat



  '#clock-cells':

    const: 1



  '#reset-cells':

    const: 1



  mux-controller:

    $ref: /schemas/mux/reg-mux.yaml#



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'

  - '#reset-cells'

  - mux-controller



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/imx8ulp-clock.h>



    clock-controller@2da50000 {

        compatible = "fsl,imx8ulp-sim-lpav";

        reg = <0x2da50000 0x10000>;

        clocks = <&cgc2 IMX8ULP_CLK_LPAV_BUS_DIV>,

                 <&cgc2 IMX8ULP_CLK_HIFI_DIVCORE>,

                 <&cgc2 IMX8ULP_CLK_HIFI_DIVPLAT>;

        clock-names = "bus", "core", "plat";

        #clock-cells = <1>;

        #reset-cells = <1>;



        mux-controller {

            compatible = "reg-mux";

            #mux-control-cells = <1>;

            mux-reg-masks = <0x8 0x00000200>;

        };

    };

include/dt-bindings/clock/imx8ulp-clock.h

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@@ -255,4 +255,9 @@ 


#define IMX8ULP_CLK_PCC5_END		56



/* LPAV SIM */

#define IMX8ULP_CLK_SIM_LPAV_HIFI_CORE		0

#define IMX8ULP_CLK_SIM_LPAV_HIFI_PBCLK		1

#define IMX8ULP_CLK_SIM_LPAV_HIFI_PLAT		2



#endif

include/dt-bindings/reset/fsl,imx8ulp-sim-lpav.h

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */

/*

 * Copyright 2025 NXP

 */



#ifndef DT_BINDING_RESET_IMX8ULP_SIM_LPAV_H

#define DT_BINDING_RESET_IMX8ULP_SIM_LPAV_H



#define IMX8ULP_SIM_LPAV_HIFI4_DSP_DBG_RST	0

#define IMX8ULP_SIM_LPAV_HIFI4_DSP_RST		1

#define IMX8ULP_SIM_LPAV_HIFI4_DSP_STALL	2

#define IMX8ULP_SIM_LPAV_DSI_RST_BYTE_N		3

#define IMX8ULP_SIM_LPAV_DSI_RST_ESC_N		4

#define IMX8ULP_SIM_LPAV_DSI_RST_DPI_N		5



#endif /* DT_BINDING_RESET_IMX8ULP_SIM_LPAV_H */