Commit 3b6ad2a4 authored by Anand Moon's avatar Anand Moon Committed by Neil Armstrong
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arm64: dts: amlogic: Add cache information to the Amlogic AXG SoCS 



As per the AXG datasheet add missing cache information to the Amlogic AXG
SoC.

- Each Cortex-A53 core has 32KB of L1 instruction cache available and
	32KB of L1 data cache available.
- Along with 512KB Unified L2 cache.

Cache memory significantly reduces the time it takes for the CPU
to access data and instructions, leading to faster program execution
and overall system responsiveness.

Signed-off-by: default avatarAnand Moon <linux.amoon@gmail.com>
Link: https://lore.kernel.org/r/20250825065240.22577-5-linux.amoon@gmail.com


Signed-off-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
parent a4428e52

arch/arm64/boot/dts/amlogic/meson-axg.dtsi

+21 −0
Original line number Diff line number Diff line
@@ -83,6 +83,12 @@ cpu1: cpu@1 { 
			compatible = "arm,cortex-a53";

			reg = <0x0 0x1>;

			enable-method = "psci";

			d-cache-line-size = <32>;

			d-cache-size = <0x8000>;

			d-cache-sets = <32>;

			i-cache-line-size = <32>;

			i-cache-size = <0x8000>;

			i-cache-sets = <32>;

			next-level-cache = <&l2>;

			clocks = <&scpi_dvfs 0>;

			dynamic-power-coefficient = <140>;
@@ -94,6 +100,12 @@ cpu2: cpu@2 { 
			compatible = "arm,cortex-a53";

			reg = <0x0 0x2>;

			enable-method = "psci";

			d-cache-line-size = <32>;

			d-cache-size = <0x8000>;

			d-cache-sets = <32>;

			i-cache-line-size = <32>;

			i-cache-size = <0x8000>;

			i-cache-sets = <32>;

			next-level-cache = <&l2>;

			clocks = <&scpi_dvfs 0>;

			dynamic-power-coefficient = <140>;
@@ -105,6 +117,12 @@ cpu3: cpu@3 { 
			compatible = "arm,cortex-a53";

			reg = <0x0 0x3>;

			enable-method = "psci";

			d-cache-line-size = <32>;

			d-cache-size = <0x8000>;

			d-cache-sets = <32>;

			i-cache-line-size = <32>;

			i-cache-size = <0x8000>;

			i-cache-sets = <32>;

			next-level-cache = <&l2>;

			clocks = <&scpi_dvfs 0>;

			dynamic-power-coefficient = <140>;
@@ -115,6 +133,9 @@ l2: l2-cache0 { 
			compatible = "cache";

			cache-level = <2>;

			cache-unified;

			cache-size = <0x80000>; /* L2. 512 KB */

			cache-line-size = <64>;

			cache-sets = <512>;

		};

	};