Commit 3b85d5f8 authored by Vimlesh Kumar's avatar Vimlesh Kumar Committed by Jakub Kicinski
Browse files

octeon_ep: reset firmware ready status 



Add support to reset firmware ready status
when the driver is removed(either in unload
or unbind)

Signed-off-by: default avatarSathesh Edara <sedara@marvell.com>
Signed-off-by: default avatarShinas Rasheed <srasheed@marvell.com>
Signed-off-by: default avatarVimlesh Kumar <vimleshk@marvell.com>
Reviewed-by: default avatarSimon Horman <horms@kernel.org>
Link: https://patch.msgid.link/20260115092048.870237-1-vimleshk@marvell.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 3d4375c2

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

+26 −0
Original line number Diff line number Diff line
@@ -637,6 +637,19 @@ static int octep_soft_reset_cn93_pf(struct octep_device *oct) 


	octep_write_csr64(oct, CN93_SDP_WIN_WR_MASK_REG, 0xFF);



	/* Firmware status CSR is supposed to be cleared by

	 * core domain reset, but due to a hw bug, it is not.

	 * Set it to RUNNING right before reset so that it is not

	 * left in READY (1) state after a reset.  This is required

	 * in addition to the early setting to handle the case where

	 * the OcteonTX is unexpectedly reset, reboots, and then

	 * the module is removed.

	 */

	OCTEP_PCI_WIN_WRITE(oct,

			    CN9K_PEMX_PFX_CSX_PFCFGX(0,

						     0, CN9K_PCIEEP_VSECST_CTL),

			    FW_STATUS_DOWNING);



	/* Set core domain reset bit */

	OCTEP_PCI_WIN_WRITE(oct, CN93_RST_CORE_DOMAIN_W1S, 1);

	/* Wait for 100ms as Octeon resets. */
@@ -894,4 +907,17 @@ void octep_device_setup_cn93_pf(struct octep_device *oct) 


	octep_init_config_cn93_pf(oct);

	octep_configure_ring_mapping_cn93_pf(oct);



	if (oct->chip_id == OCTEP_PCI_DEVICE_ID_CN98_PF)

		return;



	/* Firmware status CSR is supposed to be cleared by

	 * core domain reset, but due to IPBUPEM-38842, it is not.

	 * Set it to RUNNING early in boot, so that unexpected resets

	 * leave it in a state that is not READY (1).

	 */

	OCTEP_PCI_WIN_WRITE(oct,

			    CN9K_PEMX_PFX_CSX_PFCFGX(0,

						     0, CN9K_PCIEEP_VSECST_CTL),

			    FW_STATUS_RUNNING);

}

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

+1 −1
Original line number Diff line number Diff line
@@ -660,7 +660,7 @@ static int octep_soft_reset_cnxk_pf(struct octep_device *oct) 
	 * the module is removed.

	 */

	OCTEP_PCI_WIN_WRITE(oct, CNXK_PEMX_PFX_CSX_PFCFGX(0, 0, CNXK_PCIEEP_VSECST_CTL),

			    FW_STATUS_RUNNING);

			    FW_STATUS_DOWNING);



	/* Set chip domain reset bit */

	OCTEP_PCI_WIN_WRITE(oct, CNXK_RST_CHIP_DOMAIN_W1S, 1);

drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h

+30 −0
Original line number Diff line number Diff line
@@ -5,6 +5,8 @@ 
 *

 */



#include <linux/bitfield.h>



#ifndef _OCTEP_REGS_CN9K_PF_H_

#define _OCTEP_REGS_CN9K_PF_H_
@@ -383,6 +385,34 @@ 
/* bit 1 for firmware heartbeat interrupt */

#define CN93_SDP_EPF_OEI_RINT_DATA_BIT_HBEAT	BIT_ULL(1)



#define FW_STATUS_DOWNING      0ULL

#define FW_STATUS_RUNNING      2ULL



#define CN9K_PEM_GENMASK BIT_ULL(36)

#define CN9K_PF_GENMASK GENMASK_ULL(21, 18)

#define CN9K_PFX_CSX_PFCFGX_SHADOW_BIT BIT_ULL(16)

#define CN9K_PFX_CSX_PFCFGX_BASE_ADDR (0x8e0000008000ULL)

#define CN9K_4BYTE_ALIGNED_ADDRESS_OFFSET(offset) ((offset) & BIT_ULL(2))

#define CN9K_PEMX_PFX_CSX_PFCFGX cn9k_pemx_pfx_csx_pfcfgx



static inline u64 cn9k_pemx_pfx_csx_pfcfgx(u64 pem, u32 pf, u32 offset)

{

	u32 shadow_addr_bit, pf_addr_bits, aligned_offset;

	u64 pem_addr_bits;



	pem_addr_bits = FIELD_PREP(CN9K_PEM_GENMASK, pem);

	pf_addr_bits = FIELD_PREP(CN9K_PF_GENMASK, pf);

	shadow_addr_bit = CN9K_PFX_CSX_PFCFGX_SHADOW_BIT & (offset);

	aligned_offset = rounddown((offset), 8);



	return (CN9K_PFX_CSX_PFCFGX_BASE_ADDR | pem_addr_bits

		| pf_addr_bits | shadow_addr_bit | aligned_offset)

		+ CN9K_4BYTE_ALIGNED_ADDRESS_OFFSET(offset);

}



/* Register defines for use with CN9K_PEMX_PFX_CSX_PFCFGX */

#define CN9K_PCIEEP_VSECST_CTL  0x4D0



#define CN93_PEM_BAR4_INDEX            7

#define CN93_PEM_BAR4_INDEX_SIZE       0x400000ULL

#define CN93_PEM_BAR4_INDEX_OFFSET     (CN93_PEM_BAR4_INDEX * CN93_PEM_BAR4_INDEX_SIZE)

drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h

+1 −0
Original line number Diff line number Diff line
@@ -396,6 +396,7 @@ 
#define CNXK_SDP_EPF_OEI_RINT_DATA_BIT_MBOX	BIT_ULL(0)

/* bit 1 for firmware heartbeat interrupt */

#define CNXK_SDP_EPF_OEI_RINT_DATA_BIT_HBEAT	BIT_ULL(1)

#define FW_STATUS_DOWNING      0ULL

#define FW_STATUS_RUNNING      2ULL

#define CNXK_PEMX_PFX_CSX_PFCFGX(pem, pf, offset)      ({ typeof(offset) _off = (offset); \

							  ((0x8e0000008000 | \