Commit 3b98fd0e authored by Yihan Zhu's avatar Yihan Zhu Committed by Alex Deucher
Browse files

drm/amd/display: fix dppclk rcg poweron check 



[WHY & HOW]
dppclk rcg power down will flip the poweron flag in the cache to cause dppclk rcg will never
run the rcg ungate sequence in some condition. Wait 10us to let dpp dto fully ramp.

Reviewed-by: default avatarOvidiu (Ovi) Bunea <ovidiu.bunea@amd.com>
Reviewed-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: default avatarYihan Zhu <Yihan.Zhu@amd.com>
Signed-off-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b466ad55

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

+5 −1
Original line number Diff line number Diff line
@@ -1187,6 +1187,7 @@ static void dccg35_update_dpp_dto(struct dccg *dccg, int dpp_inst, 
		/*we have this in hwss: disable_plane*/

		//dccg35_set_dppclk_rcg(dccg, dpp_inst, true);

	}

	udelay(10);

	dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;

}
@@ -1676,7 +1677,7 @@ static void dccg35_dpp_root_clock_control( 
{

	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);



	if (dccg->dpp_clock_gated[dpp_inst] == clock_on)

	if (dccg->dpp_clock_gated[dpp_inst] != clock_on)

		return;



	if (clock_on) {
@@ -1697,6 +1698,9 @@ static void dccg35_dpp_root_clock_control( 
		//dccg35_set_dppclk_rcg(dccg, dpp_inst, true);

	}



	// wait for clock to fully ramp

	udelay(10);



	dccg->dpp_clock_gated[dpp_inst] = !clock_on;

	DC_LOG_DEBUG("%s: dpp_inst(%d) clock_on = %d\n", __func__, dpp_inst, clock_on);

}