Unverified Commit 3ba5a615 authored by Rafał Miłecki's avatar Rafał Miłecki Committed by AngeloGioacchino Del Regno
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arm64: dts: mediatek: mt7622: fix clock controllers 



1. Drop unneeded "syscon"s (bindings were updated recently)
2. Use "clock-controller" in nodenames
3. Add missing "#clock-cells"

Fixes: d7167881 ("arm64: dts: mt7622: add clock controller device nodes")
Fixes: e9b65ecb ("arm64: dts: mediatek: mt7622: introduce nodes for Wireless Ethernet Dispatch")
Signed-off-by: default avatarRafał Miłecki <rafal@milecki.pl>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20240317221050.18595-2-zajec5@gmail.com


Signed-off-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
parent 366940c8

arch/arm64/boot/dts/mediatek/mt7622.dtsi

+12 −15
Original line number Diff line number Diff line
@@ -283,16 +283,14 @@ thermal_calibration: calib@198 { 
		};

	};



	apmixedsys: apmixedsys@10209000 {

		compatible = "mediatek,mt7622-apmixedsys",

			     "syscon";

	apmixedsys: clock-controller@10209000 {

		compatible = "mediatek,mt7622-apmixedsys";

		reg = <0 0x10209000 0 0x1000>;

		#clock-cells = <1>;

	};



	topckgen: topckgen@10210000 {

		compatible = "mediatek,mt7622-topckgen",

			     "syscon";

	topckgen: clock-controller@10210000 {

		compatible = "mediatek,mt7622-topckgen";

		reg = <0 0x10210000 0 0x1000>;

		#clock-cells = <1>;

	};
@@ -734,9 +732,8 @@ wmac: wmac@18000000 { 
		power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;

	};



	ssusbsys: ssusbsys@1a000000 {

		compatible = "mediatek,mt7622-ssusbsys",

			     "syscon";

	ssusbsys: clock-controller@1a000000 {

		compatible = "mediatek,mt7622-ssusbsys";

		reg = <0 0x1a000000 0 0x1000>;

		#clock-cells = <1>;

		#reset-cells = <1>;
@@ -793,9 +790,8 @@ u2port1: usb-phy@1a0c5000 { 
		};

	};



	pciesys: pciesys@1a100800 {

		compatible = "mediatek,mt7622-pciesys",

			     "syscon";

	pciesys: clock-controller@1a100800 {

		compatible = "mediatek,mt7622-pciesys";

		reg = <0 0x1a100800 0 0x1000>;

		#clock-cells = <1>;

		#reset-cells = <1>;
@@ -921,12 +917,13 @@ sata_port: sata-phy@1a243000 { 
		};

	};



	hifsys: syscon@1af00000 {

		compatible = "mediatek,mt7622-hifsys", "syscon";

	hifsys: clock-controller@1af00000 {

		compatible = "mediatek,mt7622-hifsys";

		reg = <0 0x1af00000 0 0x70>;

		#clock-cells = <1>;

	};



	ethsys: syscon@1b000000 {

	ethsys: clock-controller@1b000000 {

		compatible = "mediatek,mt7622-ethsys",

			     "syscon";

		reg = <0 0x1b000000 0 0x1000>;