Commit 3baf0273 authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
Browse files

clk: renesas: r9a09g047: Add CA55 core clocks 



Add CA55 core clocks which are derived from PLLCA55.

Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/20241213123550.289193-4-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent bb6a9aaf

drivers/clk/renesas/r9a09g047-cpg.c

+16 −0
Original line number Diff line number Diff line
@@ -37,6 +37,14 @@ enum clk_ids { 
	MOD_CLK_BASE,

};



static const struct clk_div_table dtable_1_8[] = {

	{0, 1},

	{1, 2},

	{2, 4},

	{3, 8},

	{0, 0},

};



static const struct clk_div_table dtable_2_64[] = {

	{0, 2},

	{1, 4},
@@ -65,6 +73,14 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = { 


	/* Core Clocks */

	DEF_FIXED("sys_0_pclk", R9A09G047_SYS_0_PCLK, CLK_QEXTAL, 1, 1),

	DEF_DDIV("ca55_0_coreclk0", R9A09G047_CA55_0_CORECLK0, CLK_PLLCA55,

		 CDDIV1_DIVCTL0, dtable_1_8),

	DEF_DDIV("ca55_0_coreclk1", R9A09G047_CA55_0_CORECLK1, CLK_PLLCA55,

		 CDDIV1_DIVCTL1, dtable_1_8),

	DEF_DDIV("ca55_0_coreclk2", R9A09G047_CA55_0_CORECLK2, CLK_PLLCA55,

		 CDDIV1_DIVCTL2, dtable_1_8),

	DEF_DDIV("ca55_0_coreclk3", R9A09G047_CA55_0_CORECLK3, CLK_PLLCA55,

		 CDDIV1_DIVCTL3, dtable_1_8),

	DEF_FIXED("iotop_0_shclk", R9A09G047_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),

};