Commit 3be5262e authored by Harry Wentland's avatar Harry Wentland Committed by Alex Deucher
Browse files

drm/amd/display: Rename more dc_surface stuff to plane_state 



Signed-off-by: default avatarHarry Wentland <harry.wentland@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 0971c40e

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+145 −143
Original line number Diff line number Diff line
@@ -70,7 +70,7 @@ 
#include "i2caux_interface.h"





static enum drm_plane_type dm_surfaces_type_default[AMDGPU_MAX_PLANES] = {

static enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = {

	DRM_PLANE_TYPE_PRIMARY,

	DRM_PLANE_TYPE_PRIMARY,

	DRM_PLANE_TYPE_PRIMARY,
@@ -79,14 +79,14 @@ static enum drm_plane_type dm_surfaces_type_default[AMDGPU_MAX_PLANES] = { 
	DRM_PLANE_TYPE_PRIMARY,

};



static enum drm_plane_type dm_surfaces_type_carizzo[AMDGPU_MAX_PLANES] = {

static enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = {

	DRM_PLANE_TYPE_PRIMARY,

	DRM_PLANE_TYPE_PRIMARY,

	DRM_PLANE_TYPE_PRIMARY,

	DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */

};



static enum drm_plane_type dm_surfaces_type_stoney[AMDGPU_MAX_PLANES] = {

static enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = {

	DRM_PLANE_TYPE_PRIMARY,

	DRM_PLANE_TYPE_PRIMARY,

	DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */
@@ -1285,11 +1285,11 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) 
		return -1;

	}



	for (i = 0; i < dm->dc->caps.max_surfaces; i++) {

	for (i = 0; i < dm->dc->caps.max_planes; i++) {

		mode_info->planes[i] = kzalloc(sizeof(struct amdgpu_plane),

								 GFP_KERNEL);

		if (!mode_info->planes[i]) {

			DRM_ERROR("KMS: Failed to allocate surface\n");

			DRM_ERROR("KMS: Failed to allocate plane\n");

			goto fail_free_planes;

		}

		mode_info->planes[i]->base.type = mode_info->plane_type[i];
@@ -1389,7 +1389,7 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) 
fail_free_connector:

	kfree(aconnector);

fail_free_planes:

	for (i = 0; i < dm->dc->caps.max_surfaces; i++)

	for (i = 0; i < dm->dc->caps.max_planes; i++)

		kfree(mode_info->planes[i]);

	return -1;

}
@@ -1518,52 +1518,52 @@ static int dm_early_init(void *handle) 
		adev->mode_info.num_crtc = 6;

		adev->mode_info.num_hpd = 6;

		adev->mode_info.num_dig = 6;

		adev->mode_info.plane_type = dm_surfaces_type_default;

		adev->mode_info.plane_type = dm_plane_type_default;

		break;

	case CHIP_FIJI:

	case CHIP_TONGA:

		adev->mode_info.num_crtc = 6;

		adev->mode_info.num_hpd = 6;

		adev->mode_info.num_dig = 7;

		adev->mode_info.plane_type = dm_surfaces_type_default;

		adev->mode_info.plane_type = dm_plane_type_default;

		break;

	case CHIP_CARRIZO:

		adev->mode_info.num_crtc = 3;

		adev->mode_info.num_hpd = 6;

		adev->mode_info.num_dig = 9;

		adev->mode_info.plane_type = dm_surfaces_type_carizzo;

		adev->mode_info.plane_type = dm_plane_type_carizzo;

		break;

	case CHIP_STONEY:

		adev->mode_info.num_crtc = 2;

		adev->mode_info.num_hpd = 6;

		adev->mode_info.num_dig = 9;

		adev->mode_info.plane_type = dm_surfaces_type_stoney;

		adev->mode_info.plane_type = dm_plane_type_stoney;

		break;

	case CHIP_POLARIS11:

	case CHIP_POLARIS12:

		adev->mode_info.num_crtc = 5;

		adev->mode_info.num_hpd = 5;

		adev->mode_info.num_dig = 5;

		adev->mode_info.plane_type = dm_surfaces_type_default;

		adev->mode_info.plane_type = dm_plane_type_default;

		break;

	case CHIP_POLARIS10:

		adev->mode_info.num_crtc = 6;

		adev->mode_info.num_hpd = 6;

		adev->mode_info.num_dig = 6;

		adev->mode_info.plane_type = dm_surfaces_type_default;

		adev->mode_info.plane_type = dm_plane_type_default;

		break;

	case CHIP_VEGA10:

		adev->mode_info.num_crtc = 6;

		adev->mode_info.num_hpd = 6;

		adev->mode_info.num_dig = 6;

		adev->mode_info.plane_type = dm_surfaces_type_default;

		adev->mode_info.plane_type = dm_plane_type_default;

		break;

#if defined(CONFIG_DRM_AMD_DC_DCN1_0)

	case CHIP_RAVEN:

		adev->mode_info.num_crtc = 4;

		adev->mode_info.num_hpd = 4;

		adev->mode_info.num_dig = 4;

		adev->mode_info.plane_type = dm_surfaces_type_default;

		adev->mode_info.plane_type = dm_plane_type_default;

		break;

#endif

	default:
@@ -1821,50 +1821,50 @@ static int dm_crtc_cursor_move(struct drm_crtc *crtc, 


static bool fill_rects_from_plane_state(

	const struct drm_plane_state *state,

	struct dc_plane_state *surface)

	struct dc_plane_state *plane_state)

{

	surface->src_rect.x = state->src_x >> 16;

	surface->src_rect.y = state->src_y >> 16;

	plane_state->src_rect.x = state->src_x >> 16;

	plane_state->src_rect.y = state->src_y >> 16;

	/*we ignore for now mantissa and do not to deal with floating pixels :(*/

	surface->src_rect.width = state->src_w >> 16;

	plane_state->src_rect.width = state->src_w >> 16;



	if (surface->src_rect.width == 0)

	if (plane_state->src_rect.width == 0)

		return false;



	surface->src_rect.height = state->src_h >> 16;

	if (surface->src_rect.height == 0)

	plane_state->src_rect.height = state->src_h >> 16;

	if (plane_state->src_rect.height == 0)

		return false;



	surface->dst_rect.x = state->crtc_x;

	surface->dst_rect.y = state->crtc_y;

	plane_state->dst_rect.x = state->crtc_x;

	plane_state->dst_rect.y = state->crtc_y;



	if (state->crtc_w == 0)

		return false;



	surface->dst_rect.width = state->crtc_w;

	plane_state->dst_rect.width = state->crtc_w;



	if (state->crtc_h == 0)

		return false;



	surface->dst_rect.height = state->crtc_h;

	plane_state->dst_rect.height = state->crtc_h;



	surface->clip_rect = surface->dst_rect;

	plane_state->clip_rect = plane_state->dst_rect;



	switch (state->rotation & DRM_MODE_ROTATE_MASK) {

	case DRM_MODE_ROTATE_0:

		surface->rotation = ROTATION_ANGLE_0;

		plane_state->rotation = ROTATION_ANGLE_0;

		break;

	case DRM_MODE_ROTATE_90:

		surface->rotation = ROTATION_ANGLE_90;

		plane_state->rotation = ROTATION_ANGLE_90;

		break;

	case DRM_MODE_ROTATE_180:

		surface->rotation = ROTATION_ANGLE_180;

		plane_state->rotation = ROTATION_ANGLE_180;

		break;

	case DRM_MODE_ROTATE_270:

		surface->rotation = ROTATION_ANGLE_270;

		plane_state->rotation = ROTATION_ANGLE_270;

		break;

	default:

		surface->rotation = ROTATION_ANGLE_0;

		plane_state->rotation = ROTATION_ANGLE_0;

		break;

	}
@@ -1896,7 +1896,7 @@ static int get_fb_info( 


static int fill_plane_attributes_from_fb(

	struct amdgpu_device *adev,

	struct dc_plane_state *surface,

	struct dc_plane_state *plane_state,

	const struct amdgpu_framebuffer *amdgpu_fb, bool addReq)

{

	uint64_t tiling_flags;
@@ -1916,28 +1916,28 @@ static int fill_plane_attributes_from_fb( 


	switch (fb->format->format) {

	case DRM_FORMAT_C8:

		surface->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;

		plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;

		break;

	case DRM_FORMAT_RGB565:

		surface->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;

		plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;

		break;

	case DRM_FORMAT_XRGB8888:

	case DRM_FORMAT_ARGB8888:

		surface->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;

		plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;

		break;

	case DRM_FORMAT_XRGB2101010:

	case DRM_FORMAT_ARGB2101010:

		surface->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;

		plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;

		break;

	case DRM_FORMAT_XBGR2101010:

	case DRM_FORMAT_ABGR2101010:

		surface->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;

		plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;

		break;

	case DRM_FORMAT_NV21:

		surface->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;

		plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;

		break;

	case DRM_FORMAT_NV12:

		surface->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;

		plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;

		break;

	default:

		DRM_ERROR("Unsupported screen format %s\n",
@@ -1945,45 +1945,45 @@ static int fill_plane_attributes_from_fb( 
		return -EINVAL;

	}



	if (surface->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {

		surface->address.type = PLN_ADDR_TYPE_GRAPHICS;

		surface->address.grph.addr.low_part = lower_32_bits(fb_location);

		surface->address.grph.addr.high_part = upper_32_bits(fb_location);

		surface->plane_size.grph.surface_size.x = 0;

		surface->plane_size.grph.surface_size.y = 0;

		surface->plane_size.grph.surface_size.width = fb->width;

		surface->plane_size.grph.surface_size.height = fb->height;

		surface->plane_size.grph.surface_pitch =

	if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {

		plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS;

		plane_state->address.grph.addr.low_part = lower_32_bits(fb_location);

		plane_state->address.grph.addr.high_part = upper_32_bits(fb_location);

		plane_state->plane_size.grph.surface_size.x = 0;

		plane_state->plane_size.grph.surface_size.y = 0;

		plane_state->plane_size.grph.surface_size.width = fb->width;

		plane_state->plane_size.grph.surface_size.height = fb->height;

		plane_state->plane_size.grph.surface_pitch =

				fb->pitches[0] / fb->format->cpp[0];

		/* TODO: unhardcode */

		surface->color_space = COLOR_SPACE_SRGB;

		plane_state->color_space = COLOR_SPACE_SRGB;



	} else {

		awidth = ALIGN(fb->width, 64);

		surface->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;

		surface->address.video_progressive.luma_addr.low_part

		plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;

		plane_state->address.video_progressive.luma_addr.low_part

						= lower_32_bits(fb_location);

		surface->address.video_progressive.chroma_addr.low_part

		plane_state->address.video_progressive.chroma_addr.low_part

						= lower_32_bits(fb_location) +

							(awidth * fb->height);

		surface->plane_size.video.luma_size.x = 0;

		surface->plane_size.video.luma_size.y = 0;

		surface->plane_size.video.luma_size.width = awidth;

		surface->plane_size.video.luma_size.height = fb->height;

		plane_state->plane_size.video.luma_size.x = 0;

		plane_state->plane_size.video.luma_size.y = 0;

		plane_state->plane_size.video.luma_size.width = awidth;

		plane_state->plane_size.video.luma_size.height = fb->height;

		/* TODO: unhardcode */

		surface->plane_size.video.luma_pitch = awidth;

		plane_state->plane_size.video.luma_pitch = awidth;



		surface->plane_size.video.chroma_size.x = 0;

		surface->plane_size.video.chroma_size.y = 0;

		surface->plane_size.video.chroma_size.width = awidth;

		surface->plane_size.video.chroma_size.height = fb->height;

		surface->plane_size.video.chroma_pitch = awidth / 2;

		plane_state->plane_size.video.chroma_size.x = 0;

		plane_state->plane_size.video.chroma_size.y = 0;

		plane_state->plane_size.video.chroma_size.width = awidth;

		plane_state->plane_size.video.chroma_size.height = fb->height;

		plane_state->plane_size.video.chroma_pitch = awidth / 2;



		/* TODO: unhardcode */

		surface->color_space = COLOR_SPACE_YCBCR709;

		plane_state->color_space = COLOR_SPACE_YCBCR709;

	}



	memset(&surface->tiling_info, 0, sizeof(surface->tiling_info));

	memset(&plane_state->tiling_info, 0, sizeof(plane_state->tiling_info));



	/* Fill GFX8 params */

	if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
@@ -1996,51 +1996,51 @@ static int fill_plane_attributes_from_fb( 
		num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);



		/* XXX fix me for VI */

		surface->tiling_info.gfx8.num_banks = num_banks;

		surface->tiling_info.gfx8.array_mode =

		plane_state->tiling_info.gfx8.num_banks = num_banks;

		plane_state->tiling_info.gfx8.array_mode =

				DC_ARRAY_2D_TILED_THIN1;

		surface->tiling_info.gfx8.tile_split = tile_split;

		surface->tiling_info.gfx8.bank_width = bankw;

		surface->tiling_info.gfx8.bank_height = bankh;

		surface->tiling_info.gfx8.tile_aspect = mtaspect;

		surface->tiling_info.gfx8.tile_mode =

		plane_state->tiling_info.gfx8.tile_split = tile_split;

		plane_state->tiling_info.gfx8.bank_width = bankw;

		plane_state->tiling_info.gfx8.bank_height = bankh;

		plane_state->tiling_info.gfx8.tile_aspect = mtaspect;

		plane_state->tiling_info.gfx8.tile_mode =

				DC_ADDR_SURF_MICRO_TILING_DISPLAY;

	} else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)

			== DC_ARRAY_1D_TILED_THIN1) {

		surface->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;

		plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;

	}



	surface->tiling_info.gfx8.pipe_config =

	plane_state->tiling_info.gfx8.pipe_config =

			AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);



	if (adev->asic_type == CHIP_VEGA10 ||

	    adev->asic_type == CHIP_RAVEN) {

		/* Fill GFX9 params */

		surface->tiling_info.gfx9.num_pipes =

		plane_state->tiling_info.gfx9.num_pipes =

			adev->gfx.config.gb_addr_config_fields.num_pipes;

		surface->tiling_info.gfx9.num_banks =

		plane_state->tiling_info.gfx9.num_banks =

			adev->gfx.config.gb_addr_config_fields.num_banks;

		surface->tiling_info.gfx9.pipe_interleave =

		plane_state->tiling_info.gfx9.pipe_interleave =

			adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;

		surface->tiling_info.gfx9.num_shader_engines =

		plane_state->tiling_info.gfx9.num_shader_engines =

			adev->gfx.config.gb_addr_config_fields.num_se;

		surface->tiling_info.gfx9.max_compressed_frags =

		plane_state->tiling_info.gfx9.max_compressed_frags =

			adev->gfx.config.gb_addr_config_fields.max_compress_frags;

		surface->tiling_info.gfx9.num_rb_per_se =

		plane_state->tiling_info.gfx9.num_rb_per_se =

			adev->gfx.config.gb_addr_config_fields.num_rb_per_se;

		surface->tiling_info.gfx9.swizzle =

		plane_state->tiling_info.gfx9.swizzle =

			AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);

		surface->tiling_info.gfx9.shaderEnable = 1;

		plane_state->tiling_info.gfx9.shaderEnable = 1;

	}



	surface->visible = true;

	surface->scaling_quality.h_taps_c = 0;

	surface->scaling_quality.v_taps_c = 0;

	plane_state->visible = true;

	plane_state->scaling_quality.h_taps_c = 0;

	plane_state->scaling_quality.v_taps_c = 0;



	/* is this needed? is surface zeroed at allocation? */

	surface->scaling_quality.h_taps = 0;

	surface->scaling_quality.v_taps = 0;

	surface->stereo_format = PLANE_STEREO_FORMAT_NONE;

	/* is this needed? is plane_state zeroed at allocation? */

	plane_state->scaling_quality.h_taps = 0;

	plane_state->scaling_quality.v_taps = 0;

	plane_state->stereo_format = PLANE_STEREO_FORMAT_NONE;



	return ret;
@@ -2050,7 +2050,7 @@ static int fill_plane_attributes_from_fb( 


static void fill_gamma_from_crtc_state(

	const struct drm_crtc_state *crtc_state,

	struct dc_plane_state *dc_surface)

	struct dc_plane_state *plane_state)

{

	int i;

	struct dc_gamma *gamma;
@@ -2069,12 +2069,12 @@ static void fill_gamma_from_crtc_state( 
		gamma->blue[i] = lut[i].blue;

	}



	dc_surface->gamma_correction = gamma;

	plane_state->gamma_correction = gamma;

}



static int fill_plane_attributes(

			struct amdgpu_device *adev,

			struct dc_plane_state *surface,

			struct dc_plane_state *dc_plane_state,

			struct drm_plane_state *plane_state,

			struct drm_crtc_state *crtc_state,

			bool addrReq)
@@ -2085,12 +2085,12 @@ static int fill_plane_attributes( 
	struct dc_transfer_func *input_tf;

	int ret = 0;



	if (!fill_rects_from_plane_state(plane_state, surface))

	if (!fill_rects_from_plane_state(plane_state, dc_plane_state))

		return -EINVAL;



	ret = fill_plane_attributes_from_fb(

		crtc->dev->dev_private,

		surface,

		dc_plane_state,

		amdgpu_fb,

		addrReq);
@@ -2105,11 +2105,11 @@ static int fill_plane_attributes( 
	input_tf->type = TF_TYPE_PREDEFINED;

	input_tf->tf = TRANSFER_FUNCTION_SRGB;



	surface->in_transfer_func = input_tf;

	dc_plane_state->in_transfer_func = input_tf;



	/* In case of gamma set, update gamma value */

	if (crtc_state->gamma_lut)

		fill_gamma_from_crtc_state(crtc_state, surface);

		fill_gamma_from_crtc_state(crtc_state, dc_plane_state);



	return ret;

}
@@ -2991,9 +2991,9 @@ dm_drm_plane_duplicate_state(struct drm_plane *plane) 


	__drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);



	if (old_dm_plane_state->surface) {

		dm_plane_state->surface = old_dm_plane_state->surface;

		dc_surface_retain(dm_plane_state->surface);

	if (old_dm_plane_state->dc_state) {

		dm_plane_state->dc_state = old_dm_plane_state->dc_state;

		dc_plane_state_retain(dm_plane_state->dc_state);

	}



	return &dm_plane_state->base;
@@ -3004,8 +3004,8 @@ void dm_drm_plane_destroy_state(struct drm_plane *plane, 
{

	struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);



	if (dm_plane_state->surface)

		dc_surface_release(dm_plane_state->surface);

	if (dm_plane_state->dc_state)

		dc_plane_state_release(dm_plane_state->dc_state);



	__drm_atomic_helper_plane_destroy_state(state);

	kfree(dm_plane_state);
@@ -3059,18 +3059,18 @@ static int dm_plane_helper_prepare_fb( 


	amdgpu_bo_ref(rbo);



	if (dm_plane_state_new->surface &&

			dm_plane_state_old->surface != dm_plane_state_new->surface) {

		struct dc_plane_state *surface = dm_plane_state_new->surface;

	if (dm_plane_state_new->dc_state &&

			dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {

		struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;



		if (surface->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {

			surface->address.grph.addr.low_part = lower_32_bits(afb->address);

			surface->address.grph.addr.high_part = upper_32_bits(afb->address);

		if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {

			plane_state->address.grph.addr.low_part = lower_32_bits(afb->address);

			plane_state->address.grph.addr.high_part = upper_32_bits(afb->address);

		} else {

			awidth = ALIGN(new_state->fb->width, 64);

			surface->address.video_progressive.luma_addr.low_part

			plane_state->address.video_progressive.luma_addr.low_part

							= lower_32_bits(afb->address);

			surface->address.video_progressive.chroma_addr.low_part

			plane_state->address.video_progressive.chroma_addr.low_part

							= lower_32_bits(afb->address) +

								(awidth * new_state->fb->height);

		}
@@ -3159,10 +3159,10 @@ int dm_plane_atomic_check(struct drm_plane *plane, 
	struct dc *dc = adev->dm.dc;

	struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);



	if (!dm_plane_state->surface)

	if (!dm_plane_state->dc_state)

		return true;



	if (dc_validate_plane(dc, dm_plane_state->surface))

	if (dc_validate_plane(dc, dm_plane_state->dc_state))

		return 0;



	return -EINVAL;
@@ -3848,6 +3848,7 @@ static void amdgpu_dm_do_flip( 
	struct amdgpu_device *adev = crtc->dev->dev_private;

	bool async_flip = (acrtc->flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;

	struct dc_flip_addrs addr = { {0} };

	/* TODO eliminate or rename surface_update */

	struct dc_surface_update surface_updates[1] = { {0} };

	struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
@@ -3903,11 +3904,11 @@ static void amdgpu_dm_do_flip( 
	if (acrtc->base.state->event)

		prepare_flip_isr(acrtc);



	surface_updates->surface = dc_stream_get_status(acrtc_state->stream)->surfaces[0];

	surface_updates->surface = dc_stream_get_status(acrtc_state->stream)->plane_states[0];

	surface_updates->flip_addr = &addr;





	dc_update_surfaces_and_stream(adev->dm.dc, surface_updates, 1, acrtc_state->stream, NULL);

	dc_update_planes_and_stream(adev->dm.dc, surface_updates, 1, acrtc_state->stream, NULL);



	DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n",

			 __func__,
@@ -3918,7 +3919,7 @@ static void amdgpu_dm_do_flip( 
	spin_unlock_irqrestore(&crtc->dev->event_lock, flags);

}



static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state,

static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,

			struct drm_device *dev,

			struct amdgpu_display_manager *dm,

			struct drm_crtc *pcrtc,
@@ -3928,7 +3929,7 @@ static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state, 
	struct drm_plane *plane;

	struct drm_plane_state *old_plane_state;

	struct dc_stream_state *dc_stream_attach;

	struct dc_plane_state *dc_surfaces_constructed[MAX_SURFACES];

	struct dc_plane_state *plane_states_constructed[MAX_SURFACES];

	struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);

	struct dm_crtc_state *acrtc_state = to_dm_crtc_state(pcrtc->state);

	int planes_count = 0;
@@ -3956,7 +3957,8 @@ static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state, 


		spin_lock_irqsave(&crtc->dev->event_lock, flags);

		if (acrtc_attach->pflip_status != AMDGPU_FLIP_NONE) {

			DRM_ERROR("add_surface: acrtc %d, already busy\n",

			DRM_ERROR("%s: acrtc %d, already busy\n",

				  __func__,

				  acrtc_attach->crtc_id);

			spin_unlock_irqrestore(&crtc->dev->event_lock, flags);

			/* In commit tail framework this cannot happen */
@@ -3965,9 +3967,9 @@ static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state, 
		spin_unlock_irqrestore(&crtc->dev->event_lock, flags);



		if (!pflip_needed) {

			WARN_ON(!dm_plane_state->surface);

			WARN_ON(!dm_plane_state->dc_state);



			dc_surfaces_constructed[planes_count] = dm_plane_state->surface;

			plane_states_constructed[planes_count] = dm_plane_state->dc_state;



			dc_stream_attach = acrtc_state->stream;

			planes_count++;
@@ -4010,11 +4012,11 @@ static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state, 
			spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);

		}



		if (false == dc_commit_surfaces_to_stream(dm->dc,

							  dc_surfaces_constructed,

		if (false == dc_commit_planes_to_stream(dm->dc,

							plane_states_constructed,

							planes_count,

							dc_stream_attach))

			dm_error("%s: Failed to attach surface!\n", __func__);

			dm_error("%s: Failed to attach plane!\n", __func__);

	} else {

		/*TODO BUG Here should go disable planes on CRTC. */

	}
@@ -4226,16 +4228,16 @@ void amdgpu_dm_atomic_commit_tail( 


		status = dc_stream_get_status(new_acrtc_state->stream);

		WARN_ON(!status);

		WARN_ON(!status->surface_count);

		WARN_ON(!status->plane_count);



		if (!new_acrtc_state->stream)

			continue;



		/*TODO How it works with MPO ?*/

		if (!dc_commit_surfaces_to_stream(

		if (!dc_commit_planes_to_stream(

				dm->dc,

				status->surfaces,

				status->surface_count,

				status->plane_states,

				status->plane_count,

				new_acrtc_state->stream))

			dm_error("%s: Failed to update stream scaling!\n", __func__);

	}
@@ -4260,7 +4262,7 @@ void amdgpu_dm_atomic_commit_tail( 
		new_acrtc_state = to_dm_crtc_state(pcrtc->state);



		if (new_acrtc_state->stream)

			amdgpu_dm_commit_surfaces(state, dev, dm, pcrtc, &wait_for_vblank);

			amdgpu_dm_commit_planes(state, dev, dm, pcrtc, &wait_for_vblank);

	}
@@ -4375,27 +4377,27 @@ void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector 
		dm_force_atomic_commit(&aconnector->base);

}



static uint32_t add_val_sets_surface(

static uint32_t add_val_sets_plane(

	struct dc_validation_set *val_sets,

	uint32_t set_count,

	const struct dc_stream_state *stream,

	struct dc_plane_state *surface)

	struct dc_plane_state *plane_state)

{

	uint32_t i = 0, j = 0;



	while (i < set_count) {

		if (val_sets[i].stream == stream) {

			while (val_sets[i].surfaces[j])

			while (val_sets[i].plane_states[j])

				j++;

			break;

		}

		++i;

	}



	val_sets[i].surfaces[j] = surface;

	val_sets[i].surface_count++;

	val_sets[i].plane_states[j] = plane_state;

	val_sets[i].plane_count++;



	return val_sets[i].surface_count;

	return val_sets[i].plane_count;

}



static uint32_t update_in_val_sets_stream(
@@ -4516,7 +4518,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, 


	/*

	 * This bool will be set for true for any modeset/reset

	 * or surface update which implies non fast surface update.

	 * or plane update which implies non fast surface update.

	 */

	bool lock_and_validation_needed = false;
@@ -4701,13 +4703,13 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, 


			pflip_needed = !state->allow_modeset;

			if (!pflip_needed) {

				struct dc_plane_state *surface;

				struct dc_plane_state *dc_plane_state;



				surface = dc_create_surface(dc);

				dc_plane_state = dc_create_plane_state(dc);



				ret = fill_plane_attributes(

					plane_crtc->dev->dev_private,

					surface,

					dc_plane_state,

					plane_state,

					crtc_state,

					false);
@@ -4715,15 +4717,15 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, 
					goto fail;





				if (dm_plane_state->surface)

					dc_surface_release(dm_plane_state->surface);

				if (dm_plane_state->dc_state)

					dc_plane_state_release(dm_plane_state->dc_state);



				dm_plane_state->surface = surface;

				dm_plane_state->dc_state = dc_plane_state;



				add_val_sets_surface(set,

				add_val_sets_plane(set,

						     set_count,

						     new_acrtc_state->stream,

						     surface);

						     dc_plane_state);



				lock_and_validation_needed = true;

			}

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h

+1 −1
Original line number Diff line number Diff line
@@ -196,7 +196,7 @@ struct dc_stream; 


struct dm_plane_state {

	struct drm_plane_state base;

	struct dc_plane_state *surface;

	struct dc_plane_state *dc_state;

};



struct dm_crtc_state {

drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c

+10 −10

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c

+26 −26

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/amd/display/dc/core/dc.c

+65 −65

File changed.

Preview size limit exceeded, changes collapsed.