Commit 3c466d65 authored by Bartosz Golaszewski's avatar Bartosz Golaszewski Committed by Jakub Kicinski
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net: stmmac: qcom-ethqos: enable SGMII loopback during DMA reset on sa8775p-ride-r3 



On sa8775p-ride-r3 the RX clocks from the AQR115C PHY are not available at
the time of the DMA reset. We can however extract the RX clock from the
internal SERDES block. Once the link is up, we can revert to the
previous state.

The AQR115C PHY doesn't support in-band signalling so we can count on
getting the link up notification and safely reuse existing callbacks
which are already used by another HW quirk workaround which enables the
functional clock to avoid a DMA reset due to timeout.

Only enable loopback on revision 3 of the board - check the phy_mode to
make sure.

Signed-off-by: default avatarBartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
Link: https://patch.msgid.link/20240703181500.28491-3-brgl@bgdev.pl


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 61e9be0e

drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c

+23 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ 
#define RGMII_IO_MACRO_CONFIG2		0x1C

#define RGMII_IO_MACRO_DEBUG1		0x20

#define EMAC_SYSTEM_LOW_POWER_DEBUG	0x28

#define EMAC_WRAPPER_SGMII_PHY_CNTRL1	0xf4



/* RGMII_IO_MACRO_CONFIG fields */

#define RGMII_CONFIG_FUNC_CLK_EN		BIT(30)
@@ -79,6 +80,9 @@ 
#define ETHQOS_MAC_CTRL_SPEED_MODE		BIT(14)

#define ETHQOS_MAC_CTRL_PORT_SEL		BIT(15)



/* EMAC_WRAPPER_SGMII_PHY_CNTRL1 bits */

#define SGMII_PHY_CNTRL1_SGMII_TX_TO_RX_LOOPBACK_EN	BIT(3)



#define SGMII_10M_RX_CLK_DVDR			0x31



struct ethqos_emac_por {
@@ -95,6 +99,7 @@ struct ethqos_emac_driver_data { 
	bool has_integrated_pcs;

	u32 dma_addr_width;

	struct dwmac4_addrs dwmac4_addrs;

	bool needs_sgmii_loopback;

};



struct qcom_ethqos {
@@ -114,6 +119,7 @@ struct qcom_ethqos { 
	unsigned int num_por;

	bool rgmii_config_loopback_en;

	bool has_emac_ge_3;

	bool needs_sgmii_loopback;

};



static int rgmii_readl(struct qcom_ethqos *ethqos, unsigned int offset)
@@ -191,8 +197,22 @@ ethqos_update_link_clk(struct qcom_ethqos *ethqos, unsigned int speed) 
	clk_set_rate(ethqos->link_clk, ethqos->link_clk_rate);

}



static void

qcom_ethqos_set_sgmii_loopback(struct qcom_ethqos *ethqos, bool enable)

{

	if (!ethqos->needs_sgmii_loopback ||

	    ethqos->phy_mode != PHY_INTERFACE_MODE_2500BASEX)

		return;



	rgmii_updatel(ethqos,

		      SGMII_PHY_CNTRL1_SGMII_TX_TO_RX_LOOPBACK_EN,

		      enable ? SGMII_PHY_CNTRL1_SGMII_TX_TO_RX_LOOPBACK_EN : 0,

		      EMAC_WRAPPER_SGMII_PHY_CNTRL1);

}



static void ethqos_set_func_clk_en(struct qcom_ethqos *ethqos)

{

	qcom_ethqos_set_sgmii_loopback(ethqos, true);

	rgmii_updatel(ethqos, RGMII_CONFIG_FUNC_CLK_EN,

		      RGMII_CONFIG_FUNC_CLK_EN, RGMII_IO_MACRO_CONFIG);

}
@@ -277,6 +297,7 @@ static const struct ethqos_emac_driver_data emac_v4_0_0_data = { 
	.has_emac_ge_3 = true,

	.link_clk_name = "phyaux",

	.has_integrated_pcs = true,

	.needs_sgmii_loopback = true,

	.dma_addr_width = 36,

	.dwmac4_addrs = {

		.dma_chan = 0x00008100,
@@ -682,6 +703,7 @@ static void ethqos_fix_mac_speed(void *priv, unsigned int speed, unsigned int mo 
{

	struct qcom_ethqos *ethqos = priv;



	qcom_ethqos_set_sgmii_loopback(ethqos, false);

	ethqos->speed = speed;

	ethqos_update_link_clk(ethqos, speed);

	ethqos_configure(ethqos);
@@ -820,6 +842,7 @@ static int qcom_ethqos_probe(struct platform_device *pdev) 
	ethqos->num_por = data->num_por;

	ethqos->rgmii_config_loopback_en = data->rgmii_config_loopback_en;

	ethqos->has_emac_ge_3 = data->has_emac_ge_3;

	ethqos->needs_sgmii_loopback = data->needs_sgmii_loopback;



	ethqos->link_clk = devm_clk_get(dev, data->link_clk_name ?: "rgmii");

	if (IS_ERR(ethqos->link_clk))