Commit 3c6f5afd authored by Simona Vetter's avatar Simona Vetter
Browse files

Merge tag 'amd-drm-fixes-6.10-2024-07-03' of... 

Merge tag 'amd-drm-fixes-6.10-2024-07-03' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-fixes

amd-drm-fixes-6.10-2024-07-03:

amdgpu:
- Freesync fixes
- DML1 bandwidth fix
- DCN 3.5 fixes
- DML2 fix
- Silence an UBSAN warning

radeon:
- GPUVM fix

Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240703184723.1981997-1-alexander.deucher@amd.com
parents 2879b482 d0417264

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+52 −1
Original line number Diff line number Diff line
@@ -10048,6 +10048,7 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm, 
	}



	/* Update Freesync settings. */

	reset_freesync_config_for_crtc(dm_new_crtc_state);

	get_freesync_config_for_crtc(dm_new_crtc_state,

				     dm_new_conn_state);
@@ -11181,6 +11182,49 @@ static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector, 
	return ret;

}



static void parse_edid_displayid_vrr(struct drm_connector *connector,

		struct edid *edid)

{

	u8 *edid_ext = NULL;

	int i;

	int j = 0;

	u16 min_vfreq;

	u16 max_vfreq;



	if (edid == NULL || edid->extensions == 0)

		return;



	/* Find DisplayID extension */

	for (i = 0; i < edid->extensions; i++) {

		edid_ext = (void *)(edid + (i + 1));

		if (edid_ext[0] == DISPLAYID_EXT)

			break;

	}



	if (edid_ext == NULL)

		return;



	while (j < EDID_LENGTH) {

		/* Get dynamic video timing range from DisplayID if available */

		if (EDID_LENGTH - j > 13 && edid_ext[j] == 0x25	&&

		    (edid_ext[j+1] & 0xFE) == 0 && (edid_ext[j+2] == 9)) {

			min_vfreq = edid_ext[j+9];

			if (edid_ext[j+1] & 7)

				max_vfreq = edid_ext[j+10] + ((edid_ext[j+11] & 3) << 8);

			else

				max_vfreq = edid_ext[j+10];



			if (max_vfreq && min_vfreq) {

				connector->display_info.monitor_range.max_vfreq = max_vfreq;

				connector->display_info.monitor_range.min_vfreq = min_vfreq;



				return;

			}

		}

		j++;

	}

}



static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector,

			  struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)

{
@@ -11302,6 +11346,11 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 
	if (!adev->dm.freesync_module)

		goto update;



	/* Some eDP panels only have the refresh rate range info in DisplayID */

	if ((connector->display_info.monitor_range.min_vfreq == 0 ||

	     connector->display_info.monitor_range.max_vfreq == 0))

		parse_edid_displayid_vrr(connector, edid);



	if (edid && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||

		     sink->sink_signal == SIGNAL_TYPE_EDP)) {

		bool edid_check_required = false;
@@ -11309,9 +11358,11 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 
		if (is_dp_capable_without_timing_msa(adev->dm.dc,

						     amdgpu_dm_connector)) {

			if (edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ) {

				freesync_capable = true;

				amdgpu_dm_connector->min_vfreq = connector->display_info.monitor_range.min_vfreq;

				amdgpu_dm_connector->max_vfreq = connector->display_info.monitor_range.max_vfreq;

				if (amdgpu_dm_connector->max_vfreq -

				    amdgpu_dm_connector->min_vfreq > 10)

					freesync_capable = true;

			} else {

				edid_check_required = edid->version > 1 ||

						      (edid->version == 1 &&

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

+3 −0
Original line number Diff line number Diff line
@@ -3364,6 +3364,9 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
							&mode_lib->vba.UrgentBurstFactorLumaPre[k],

							&mode_lib->vba.UrgentBurstFactorChromaPre[k],

							&mode_lib->vba.NotUrgentLatencyHidingPre[k]);



					v->cursor_bw_pre[k] = mode_lib->vba.NumberOfCursors[k] * mode_lib->vba.CursorWidth[k][0] * mode_lib->vba.CursorBPP[k][0] /

							8.0 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * v->VRatioPreY[i][j][k];

				}



				{

drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c

+1 −0
Original line number Diff line number Diff line
@@ -234,6 +234,7 @@ void dml2_init_socbb_params(struct dml2_context *dml2, const struct dc *in_dc, s 
		out->round_trip_ping_latency_dcfclk_cycles = 106;

		out->smn_latency_us = 2;

		out->dispclk_dppclk_vco_speed_mhz = 3600;

		out->pct_ideal_dram_bw_after_urgent_pixel_only = 65.0;

		break;



	}

drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.c

+1 −1
Original line number Diff line number Diff line
@@ -294,7 +294,7 @@ void dml2_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *cont 
	context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = (unsigned int)in_ctx->v20.dml_core_ctx.mp.DCFCLKDeepSleep * 1000;

	context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;



	if (in_ctx->v20.dml_core_ctx.ms.support.FCLKChangeSupport[in_ctx->v20.scratch.mode_support_params.out_lowest_state_idx] == dml_fclock_change_unsupported)

	if (in_ctx->v20.dml_core_ctx.ms.support.FCLKChangeSupport[0] == dml_fclock_change_unsupported)

		context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = false;

	else

		context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = true;

drivers/gpu/drm/amd/include/atomfirmware.h

+1 −1
Original line number Diff line number Diff line
@@ -734,7 +734,7 @@ struct atom_gpio_pin_lut_v2_1 
{

  struct  atom_common_table_header  table_header;

  /*the real number of this included in the structure is calcualted by using the (whole structure size - the header size)/size of atom_gpio_pin_lut  */

  struct  atom_gpio_pin_assignment  gpio_pin[8];

  struct  atom_gpio_pin_assignment  gpio_pin[];

};