Commit 3c7cb841 authored by Xin Li's avatar Xin Li Committed by Sean Christopherson
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x86/cpufeatures: Add a CPU feature bit for MSR immediate form instructions 



The immediate form of MSR access instructions are primarily motivated
by performance, not code size: by having the MSR number in an immediate,
it is available *much* earlier in the pipeline, which allows the
hardware much more leeway about how a particular MSR is handled.

Use a scattered CPU feature bit for MSR immediate form instructions.

Suggested-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Signed-off-by: default avatarXin Li (Intel) <xin@zytor.com>
Link: https://lore.kernel.org/r/20250805202224.1475590-2-seanjc@google.com


Signed-off-by: default avatarSean Christopherson <seanjc@google.com>
parent 6c3d4b91

arch/x86/include/asm/cpufeatures.h

+1 −0
Original line number Diff line number Diff line
@@ -495,6 +495,7 @@ 
#define X86_FEATURE_TSA_SQ_NO		(21*32+11) /* AMD CPU not vulnerable to TSA-SQ */

#define X86_FEATURE_TSA_L1_NO		(21*32+12) /* AMD CPU not vulnerable to TSA-L1 */

#define X86_FEATURE_CLEAR_CPU_BUF_VM	(21*32+13) /* Clear CPU buffers using VERW before VMRUN */

#define X86_FEATURE_MSR_IMM		(21*32+14) /* MSR immediate form instructions */



/*

 * BUG word(s)

arch/x86/kernel/cpu/scattered.c

+1 −0
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ static const struct cpuid_bit cpuid_bits[] = { 
	{ X86_FEATURE_APERFMPERF,		CPUID_ECX,  0, 0x00000006, 0 },

	{ X86_FEATURE_EPB,			CPUID_ECX,  3, 0x00000006, 0 },

	{ X86_FEATURE_INTEL_PPIN,		CPUID_EBX,  0, 0x00000007, 1 },

	{ X86_FEATURE_MSR_IMM,			CPUID_ECX,  5, 0x00000007, 1 },

	{ X86_FEATURE_APX,			CPUID_EDX, 21, 0x00000007, 1 },

	{ X86_FEATURE_RRSBA_CTRL,		CPUID_EDX,  2, 0x00000007, 2 },

	{ X86_FEATURE_BHI_CTRL,			CPUID_EDX,  4, 0x00000007, 2 },