Commit 3d0ebc36 authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull SoC fixes from Arnd Bergmann:
 "A few last minute fixes:

   - two driver fixes for samsung/google platforms, both addressing
     mistakes in changes from the 6.15 merge window

   - a revert for an allwinner devicetree change that caused problems

   - a fix for an older regression with the LEDs on Marvell Armada 3720

   - a defconfig change to enable chacha20 again after a crypto
     subsystem change in 6.15 inadventently turned it off"

* tag 'soc-fixes-6.15-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
  arm64: defconfig: Ensure CRYPTO_CHACHA20_NEON is selected
  arm64: dts: marvell: uDPU: define pinctrl state for alarm LEDs
  Revert "arm64: dts: allwinner: h6: Use RSB for AXP805 PMIC connection"
  soc: samsung: usi: prevent wrong bits inversion during unconfiguring
  firmware: exynos-acpm: check saved RX before bailing out on empty RX queue
parents 79cd8920 070d04f0
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+19 −19
Original line number Diff line number Diff line
@@ -152,28 +152,12 @@ &pio {
	vcc-pg-supply = <&reg_aldo1>;
};

&r_ir {
	linux,rc-map-name = "rc-beelink-gs1";
	status = "okay";
};

&r_pio {
	/*
	 * FIXME: We can't add that supply for now since it would
	 * create a circular dependency between pinctrl, the regulator
	 * and the RSB Bus.
	 *
	 * vcc-pl-supply = <&reg_aldo1>;
	 */
	vcc-pm-supply = <&reg_aldo1>;
};

&r_rsb {
&r_i2c {
	status = "okay";

	axp805: pmic@745 {
	axp805: pmic@36 {
		compatible = "x-powers,axp805", "x-powers,axp806";
		reg = <0x745>;
		reg = <0x36>;
		interrupt-parent = <&r_intc>;
		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
		interrupt-controller;
@@ -291,6 +275,22 @@ sw {
	};
};

&r_ir {
	linux,rc-map-name = "rc-beelink-gs1";
	status = "okay";
};

&r_pio {
	/*
	 * PL0 and PL1 are used for PMIC I2C
	 * don't enable the pl-supply else
	 * it will fail at boot
	 *
	 * vcc-pl-supply = <&reg_aldo1>;
	 */
	vcc-pm-supply = <&reg_aldo1>;
};

&spdif {
	pinctrl-names = "default";
	pinctrl-0 = <&spdif_tx_pin>;
+7 −7
Original line number Diff line number Diff line
@@ -176,16 +176,12 @@ &pio {
	vcc-pg-supply = <&reg_vcc_wifi_io>;
};

&r_ir {
	status = "okay";
};

&r_rsb {
&r_i2c {
	status = "okay";

	axp805: pmic@745 {
	axp805: pmic@36 {
		compatible = "x-powers,axp805", "x-powers,axp806";
		reg = <0x745>;
		reg = <0x36>;
		interrupt-parent = <&r_intc>;
		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
		interrupt-controller;
@@ -296,6 +292,10 @@ sw {
	};
};

&r_ir {
	status = "okay";
};

&rtc {
	clocks = <&ext_osc32k>;
};
+11 −11
Original line number Diff line number Diff line
@@ -113,20 +113,12 @@ &pio {
	vcc-pg-supply = <&reg_aldo1>;
};

&r_ir {
	status = "okay";
};

&r_pio {
	vcc-pm-supply = <&reg_bldo3>;
};

&r_rsb {
&r_i2c {
	status = "okay";

	axp805: pmic@745 {
	axp805: pmic@36 {
		compatible = "x-powers,axp805", "x-powers,axp806";
		reg = <0x745>;
		reg = <0x36>;
		interrupt-parent = <&r_intc>;
		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
		interrupt-controller;
@@ -241,6 +233,14 @@ sw {
	};
};

&r_ir {
	status = "okay";
};

&r_pio {
	vcc-pm-supply = <&reg_bldo3>;
};

&rtc {
	clocks = <&ext_osc32k>;
};
+6 −2
Original line number Diff line number Diff line
@@ -26,6 +26,8 @@ memory@0 {

	leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&spi_quad_pins>;

		led-power1 {
			label = "udpu:green:power";
@@ -82,8 +84,6 @@ &sdhci0 {

&spi0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&spi_quad_pins>;

	flash@0 {
		compatible = "jedec,spi-nor";
@@ -108,6 +108,10 @@ partition@180000 {
	};
};

&spi_quad_pins {
	function = "gpio";
};

&pinctrl_nb {
	i2c2_recovery_pins: i2c2-recovery-pins {
		groups = "i2c2";
+1 −1
Original line number Diff line number Diff line
@@ -1729,12 +1729,12 @@ CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_SECURITY=y
CONFIG_CRYPTO_USER=y
CONFIG_CRYPTO_CHACHA20=m
CONFIG_CRYPTO_TEST=m
CONFIG_CRYPTO_ECHAINIV=y
CONFIG_CRYPTO_MICHAEL_MIC=m
CONFIG_CRYPTO_ANSI_CPRNG=y
CONFIG_CRYPTO_USER_API_RNG=m
CONFIG_CRYPTO_CHACHA20_NEON=m
CONFIG_CRYPTO_GHASH_ARM64_CE=y
CONFIG_CRYPTO_SHA1_ARM64_CE=y
CONFIG_CRYPTO_SHA2_ARM64_CE=y
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