Commit 3d23ce8c authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915/cdclk: Move intel_bw_crtc_min_cdclk() handling into intel_crtc_compute_min_cdclk() 



intel_bw_crtc_min_cdclk() depends only on per-crtc state,
so there is no real point in having it complicate the global
bw_min_cdclk. Instead let's just account for it in
intel_crtc_compute_min_cdclk().

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250923171943.7319-16-ville.syrjala@linux.intel.com


Reviewed-by: default avatarMika Kahola <mika.kahola@intel.com>
parent fa7fd8eb

drivers/gpu/drm/i915/display/intel_bw.c

+4 −13
Original line number Diff line number Diff line
@@ -871,13 +871,14 @@ static unsigned int intel_bw_crtc_data_rate(const struct intel_crtc_state *crtc_ 
}



/* "Maximum Pipe Read Bandwidth" */

static int intel_bw_crtc_min_cdclk(struct intel_display *display,

				   unsigned int data_rate)

int intel_bw_crtc_min_cdclk(const struct intel_crtc_state *crtc_state)

{

	struct intel_display *display = to_intel_display(crtc_state);



	if (DISPLAY_VER(display) < 12)

		return 0;



	return DIV_ROUND_UP_ULL(mul_u32_u32(data_rate, 10), 512);

	return DIV_ROUND_UP_ULL(mul_u32_u32(intel_bw_crtc_data_rate(crtc_state), 10), 512);

}



static unsigned int intel_bw_num_active_planes(struct intel_display *display,
@@ -1292,10 +1293,6 @@ static bool intel_bw_state_changed(struct intel_display *display, 


		if (intel_dbuf_bw_changed(display, old_dbuf_bw, new_dbuf_bw))

			return true;



		if (intel_bw_crtc_min_cdclk(display, old_bw_state->data_rate[pipe]) !=

		    intel_bw_crtc_min_cdclk(display, new_bw_state->data_rate[pipe]))

			return true;

	}



	return false;
@@ -1386,16 +1383,10 @@ intel_bw_dbuf_min_cdclk(struct intel_display *display, 
int intel_bw_min_cdclk(struct intel_display *display,

		       const struct intel_bw_state *bw_state)

{

	enum pipe pipe;

	int min_cdclk;



	min_cdclk = intel_bw_dbuf_min_cdclk(display, bw_state);



	for_each_pipe(display, pipe)

		min_cdclk = max(min_cdclk,

				intel_bw_crtc_min_cdclk(display,

							bw_state->data_rate[pipe]));



	return min_cdclk;

}

drivers/gpu/drm/i915/display/intel_bw.h

+1 −0
Original line number Diff line number Diff line
@@ -29,6 +29,7 @@ intel_atomic_get_bw_state(struct intel_atomic_state *state); 
void intel_bw_init_hw(struct intel_display *display);

int intel_bw_init(struct intel_display *display);

int intel_bw_atomic_check(struct intel_atomic_state *state);

int intel_bw_crtc_min_cdclk(const struct intel_crtc_state *crtc_state);

int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,

			    bool *need_cdclk_calc);

int intel_bw_min_cdclk(struct intel_display *display,

drivers/gpu/drm/i915/display/intel_cdclk.c

+1 −0
Original line number Diff line number Diff line
@@ -2828,6 +2828,7 @@ static int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_stat 
		return 0;



	min_cdclk = intel_pixel_rate_to_cdclk(crtc_state);

	min_cdclk = max(min_cdclk, intel_bw_crtc_min_cdclk(crtc_state));

	min_cdclk = max(min_cdclk, hsw_ips_min_cdclk(crtc_state));

	min_cdclk = max(min_cdclk, intel_audio_min_cdclk(crtc_state));

	min_cdclk = max(min_cdclk, vlv_dsi_min_cdclk(crtc_state));