Commit 3d3ac202 authored by Lizhi Hou's avatar Lizhi Hou
Browse files

accel/amdxdna: Poll MPNPU_PWAITMODE after requesting firmware suspend 



After issuing a firmware suspend request, the driver must ensure that the
suspend operation has completed before proceeding. Add polling of the
MPNPU_PWAITMODE register to confirm that the firmware has fully entered
the suspended state. This prevents race conditions where subsequent
operations assume the firmware is idle before it has actually completed
its suspend sequence.

Reviewed-by: default avatarMario Limonciello (AMD) <superm1@kernel.org>
Reviewed-by: default avatarMaciej Falkowski <maciej.falkowski@linux.intel.com>
Signed-off-by: default avatarLizhi Hou <lizhi.hou@amd.com>
Link: https://patch.msgid.link/20251202165427.507414-1-lizhi.hou@amd.com
parent 439be5c5

drivers/accel/amdxdna/aie2_message.c

+8 −1
Original line number Diff line number Diff line
@@ -59,8 +59,15 @@ static int aie2_send_mgmt_msg_wait(struct amdxdna_dev_hdl *ndev, 
int aie2_suspend_fw(struct amdxdna_dev_hdl *ndev)

{

	DECLARE_AIE2_MSG(suspend, MSG_OP_SUSPEND);

	int ret;



	return aie2_send_mgmt_msg_wait(ndev, &msg);

	ret = aie2_send_mgmt_msg_wait(ndev, &msg);

	if (ret) {

		XDNA_ERR(ndev->xdna, "Failed to suspend fw, ret %d", ret);

		return ret;

	}



	return aie2_psp_waitmode_poll(ndev->psp_hdl);

}



int aie2_resume_fw(struct amdxdna_dev_hdl *ndev)

drivers/accel/amdxdna/aie2_pci.h

+2 −0
Original line number Diff line number Diff line
@@ -70,6 +70,7 @@ enum psp_reg_idx { 
	PSP_INTR_REG = PSP_NUM_IN_REGS,

	PSP_STATUS_REG,

	PSP_RESP_REG,

	PSP_PWAITMODE_REG,

	PSP_MAX_REGS /* Keep this at the end */

};
@@ -290,6 +291,7 @@ int aie2_pm_set_mode(struct amdxdna_dev_hdl *ndev, enum amdxdna_power_mode_type 
struct psp_device *aie2m_psp_create(struct drm_device *ddev, struct psp_config *conf);

int aie2_psp_start(struct psp_device *psp);

void aie2_psp_stop(struct psp_device *psp);

int aie2_psp_waitmode_poll(struct psp_device *psp);



/* aie2_error.c */

int aie2_error_async_events_alloc(struct amdxdna_dev_hdl *ndev);

drivers/accel/amdxdna/aie2_psp.c

+15 −0
Original line number Diff line number Diff line
@@ -76,6 +76,21 @@ static int psp_exec(struct psp_device *psp, u32 *reg_vals) 
	return 0;

}



int aie2_psp_waitmode_poll(struct psp_device *psp)

{

	struct amdxdna_dev *xdna = to_xdna_dev(psp->ddev);

	u32 mode_reg;

	int ret;



	ret = readx_poll_timeout(readl, PSP_REG(psp, PSP_PWAITMODE_REG), mode_reg,

				 (mode_reg & 0x1) == 1,

				 PSP_POLL_INTERVAL, PSP_POLL_TIMEOUT);

	if (ret)

		XDNA_ERR(xdna, "fw waitmode reg error, ret %d", ret);



	return ret;

}



void aie2_psp_stop(struct psp_device *psp)

{

	u32 reg_vals[PSP_NUM_IN_REGS] = { PSP_RELEASE_TMR, };

drivers/accel/amdxdna/npu1_regs.c

+2 −0
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ 
#include "amdxdna_pci_drv.h"



/* Address definition from NPU1 docs */

#define MPNPU_PWAITMODE			0x3010034

#define MPNPU_PUB_SEC_INTR		0x3010090

#define MPNPU_PUB_PWRMGMT_INTR		0x3010094

#define MPNPU_PUB_SCRATCH2		0x30100A0
@@ -92,6 +93,7 @@ static const struct amdxdna_dev_priv npu1_dev_priv = { 
		DEFINE_BAR_OFFSET(PSP_INTR_REG,   NPU1_PSP, MPNPU_PUB_SEC_INTR),

		DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU1_PSP, MPNPU_PUB_SCRATCH2),

		DEFINE_BAR_OFFSET(PSP_RESP_REG,   NPU1_PSP, MPNPU_PUB_SCRATCH3),

		DEFINE_BAR_OFFSET(PSP_PWAITMODE_REG, NPU1_PSP, MPNPU_PWAITMODE),

	},

	.smu_regs_off   = {

		DEFINE_BAR_OFFSET(SMU_CMD_REG,  NPU1_SMU, MPNPU_PUB_SCRATCH5),

drivers/accel/amdxdna/npu2_regs.c

+2 −0
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ 
#include "amdxdna_pci_drv.h"



/* NPU Public Registers on MpNPUAxiXbar (refer to Diag npu_registers.h) */

#define MPNPU_PWAITMODE                0x301003C

#define MPNPU_PUB_SEC_INTR             0x3010060

#define MPNPU_PUB_PWRMGMT_INTR         0x3010064

#define MPNPU_PUB_SCRATCH0             0x301006C
@@ -85,6 +86,7 @@ static const struct amdxdna_dev_priv npu2_dev_priv = { 
		DEFINE_BAR_OFFSET(PSP_INTR_REG,   NPU2_PSP, MP0_C2PMSG_73),

		DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU2_PSP, MP0_C2PMSG_123),

		DEFINE_BAR_OFFSET(PSP_RESP_REG,   NPU2_REG, MPNPU_PUB_SCRATCH3),

		DEFINE_BAR_OFFSET(PSP_PWAITMODE_REG, NPU2_REG, MPNPU_PWAITMODE),

	},

	.smu_regs_off   = {

		DEFINE_BAR_OFFSET(SMU_CMD_REG,  NPU2_SMU, MP1_C2PMSG_0),