Unverified Commit 3d594a64 authored by Mark Brown's avatar Mark Brown
Browse files

spi: spi-fsl-dspi: DSPI support for NXP S32G 

Merge series from James Clark <james.clark@linaro.org>:

DT and driver changes for DSPI on S32G platforms. First 3 commits are
fixes for various edge cases which also apply to other platforms.
Remaining commits add new S32G registers and device settings, some S32G
specific fixes and then finally add the DT compatibles and binding docs.

Tested in both host and target mode on S32G-VNP-RDB3 by transferring to
an external device over spi1 using spidev_test.c
parents c4592621 9a30e332

Documentation/devicetree/bindings/spi/fsl,dspi.yaml

+18 −0
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ properties: 
          - fsl,ls2080a-dspi

          - fsl,ls2085a-dspi

          - fsl,lx2160a-dspi

          - nxp,s32g2-dspi

      - items:

          - enum:

              - fsl,ls1012a-dspi
@@ -37,6 +38,9 @@ properties: 
      - items:

          - const: fsl,lx2160a-dspi

          - const: fsl,ls2085a-dspi

      - items:

          - const: nxp,s32g3-dspi

          - const: nxp,s32g2-dspi



  reg:

    maxItems: 1
@@ -114,3 +118,17 @@ examples: 
            spi-cs-hold-delay-ns = <50>;

        };

    };

  # S32G3 in target mode

  - |

    spi@401d4000 {

        compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi";

        reg = <0x401d4000 0x1000>;

        interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;

        clocks = <&clks 26>;

        clock-names = "dspi";

        spi-num-chipselects = <8>;

        bus-num = <0>;

        dmas = <&edma0 0 7>, <&edma0 0 8>;

        dma-names = "tx", "rx";

        spi-slave;

    };

drivers/spi/Kconfig

+2 −2
Original line number Diff line number Diff line
@@ -647,10 +647,10 @@ config SPI_FSL_SPI 
config SPI_FSL_DSPI

	tristate "Freescale DSPI controller"

	select REGMAP_MMIO

	depends on SOC_VF610 || SOC_LS1021A || ARCH_LAYERSCAPE || M5441x || COMPILE_TEST

	depends on ARCH_MXC || ARCH_NXP || M54541x || COMPILE_TEST

	help

	  This enables support for the Freescale DSPI controller in master

	  mode. VF610, LS1021A and ColdFire platforms uses the controller.

	  mode. S32, VF610, LS1021A and ColdFire platforms uses the controller.



config SPI_FSL_ESPI

	tristate "Freescale eSPI controller"

drivers/spi/spi-fsl-dspi.c

+233 −123
Original line number Diff line number Diff line
@@ -24,6 +24,7 @@ 


#define SPI_MCR				0x00

#define SPI_MCR_HOST			BIT(31)

#define SPI_MCR_MTFE			BIT(26)

#define SPI_MCR_PCSIS(x)		((x) << 16)

#define SPI_MCR_CLR_TXF			BIT(11)

#define SPI_MCR_CLR_RXF			BIT(10)
@@ -35,8 +36,9 @@ 
#define SPI_TCR				0x08

#define SPI_TCR_GET_TCNT(x)		(((x) & GENMASK(31, 16)) >> 16)



#define SPI_CTAR(x)			(0x0c + (((x) & GENMASK(1, 0)) * 4))

#define SPI_CTAR(x)			(0x0c + (((x) & GENMASK(2, 0)) * 4))

#define SPI_CTAR_FMSZ(x)		(((x) << 27) & GENMASK(30, 27))

#define SPI_CTAR_DBR			BIT(31)

#define SPI_CTAR_CPOL			BIT(26)

#define SPI_CTAR_CPHA			BIT(25)

#define SPI_CTAR_LSBFE			BIT(24)
@@ -93,12 +95,14 @@ 
#define SPI_TXFR1			0x40

#define SPI_TXFR2			0x44

#define SPI_TXFR3			0x48

#define SPI_TXFR4			0x4C

#define SPI_RXFR0			0x7c

#define SPI_RXFR1			0x80

#define SPI_RXFR2			0x84

#define SPI_RXFR3			0x88

#define SPI_RXFR4			0x8C



#define SPI_CTARE(x)			(0x11c + (((x) & GENMASK(1, 0)) * 4))

#define SPI_CTARE(x)			(0x11c + (((x) & GENMASK(2, 0)) * 4))

#define SPI_CTARE_FMSZE(x)		(((x) & 0x1) << 16)

#define SPI_CTARE_DTCP(x)		((x) & 0x7ff)
@@ -109,6 +113,8 @@ 


#define DMA_COMPLETION_TIMEOUT		msecs_to_jiffies(3000)



#define SPI_25MHZ			25000000



struct chip_data {

	u32			ctar_val;

};
@@ -122,6 +128,7 @@ struct fsl_dspi_devtype_data { 
	enum dspi_trans_mode	trans_mode;

	u8			max_clock_factor;

	int			fifo_size;

	const struct regmap_config *regmap;

};



enum {
@@ -135,6 +142,102 @@ enum { 
	LX2160A,

	MCF5441X,

	VF610,

	S32G,

	S32G_TARGET,

};



static const struct regmap_range dspi_yes_ranges[] = {

	regmap_reg_range(SPI_MCR, SPI_MCR),

	regmap_reg_range(SPI_TCR, SPI_CTAR(3)),

	regmap_reg_range(SPI_SR, SPI_TXFR3),

	regmap_reg_range(SPI_RXFR0, SPI_RXFR3),

	regmap_reg_range(SPI_CTARE(0), SPI_CTARE(3)),

	regmap_reg_range(SPI_SREX, SPI_SREX),

};



static const struct regmap_range s32g_dspi_yes_ranges[] = {

	regmap_reg_range(SPI_MCR, SPI_MCR),

	regmap_reg_range(SPI_TCR, SPI_CTAR(5)),

	regmap_reg_range(SPI_SR, SPI_TXFR4),

	regmap_reg_range(SPI_RXFR0, SPI_RXFR4),

	regmap_reg_range(SPI_CTARE(0), SPI_CTARE(5)),

	regmap_reg_range(SPI_SREX, SPI_SREX),

};



static const struct regmap_access_table dspi_access_table = {

	.yes_ranges	= dspi_yes_ranges,

	.n_yes_ranges	= ARRAY_SIZE(dspi_yes_ranges),

};



static const struct regmap_access_table s32g_dspi_access_table = {

	.yes_ranges	= s32g_dspi_yes_ranges,

	.n_yes_ranges	= ARRAY_SIZE(s32g_dspi_yes_ranges),

};



static const struct regmap_range dspi_volatile_ranges[] = {

	regmap_reg_range(SPI_MCR, SPI_TCR),

	regmap_reg_range(SPI_SR, SPI_SR),

	regmap_reg_range(SPI_PUSHR, SPI_RXFR4),

	regmap_reg_range(SPI_SREX, SPI_SREX),

};



static const struct regmap_access_table dspi_volatile_table = {

	.yes_ranges	= dspi_volatile_ranges,

	.n_yes_ranges	= ARRAY_SIZE(dspi_volatile_ranges),

};



enum {

	DSPI_REGMAP,

	S32G_DSPI_REGMAP,

	DSPI_XSPI_REGMAP,

	S32G_DSPI_XSPI_REGMAP,

	DSPI_PUSHR,

};



static const struct regmap_config dspi_regmap_config[] = {

	[DSPI_REGMAP] = {

		.reg_bits	= 32,

		.val_bits	= 32,

		.reg_stride	= 4,

		.max_register	= SPI_RXFR3,

		.volatile_table	= &dspi_volatile_table,

		.rd_table	= &dspi_access_table,

		.wr_table	= &dspi_access_table,

	},

	[S32G_DSPI_REGMAP] = {

		.reg_bits	= 32,

		.val_bits	= 32,

		.reg_stride	= 4,

		.max_register	= SPI_RXFR4,

		.volatile_table	= &dspi_volatile_table,

		.wr_table	= &s32g_dspi_access_table,

		.rd_table	= &s32g_dspi_access_table,

	},

	[DSPI_XSPI_REGMAP] = {

		.reg_bits	= 32,

		.val_bits	= 32,

		.reg_stride	= 4,

		.max_register	= SPI_SREX,

		.volatile_table	= &dspi_volatile_table,

		.rd_table	= &dspi_access_table,

		.wr_table	= &dspi_access_table,

	},

	[S32G_DSPI_XSPI_REGMAP] = {

		.reg_bits	= 32,

		.val_bits	= 32,

		.reg_stride	= 4,

		.max_register	= SPI_SREX,

		.volatile_table	= &dspi_volatile_table,

		.wr_table	= &s32g_dspi_access_table,

		.rd_table	= &s32g_dspi_access_table,

	},

	[DSPI_PUSHR] = {

		.name		= "pushr",

		.reg_bits	= 16,

		.val_bits	= 16,

		.reg_stride	= 2,

		.max_register	= 0x2,

	},

};



static const struct fsl_dspi_devtype_data devtype_data[] = {
@@ -142,55 +245,77 @@ static const struct fsl_dspi_devtype_data devtype_data[] = { 
		.trans_mode		= DSPI_DMA_MODE,

		.max_clock_factor	= 2,

		.fifo_size		= 4,

		.regmap			= &dspi_regmap_config[DSPI_REGMAP],

	},

	[LS1021A] = {

		/* Has A-011218 DMA erratum */

		.trans_mode		= DSPI_XSPI_MODE,

		.max_clock_factor	= 8,

		.fifo_size		= 4,

		.regmap			= &dspi_regmap_config[DSPI_XSPI_REGMAP],

	},

	[LS1012A] = {

		/* Has A-011218 DMA erratum */

		.trans_mode		= DSPI_XSPI_MODE,

		.max_clock_factor	= 8,

		.fifo_size		= 16,

		.regmap			= &dspi_regmap_config[DSPI_XSPI_REGMAP],

	},

	[LS1028A] = {

		.trans_mode		= DSPI_XSPI_MODE,

		.max_clock_factor	= 8,

		.fifo_size		= 4,

		.regmap			= &dspi_regmap_config[DSPI_XSPI_REGMAP],

	},

	[LS1043A] = {

		/* Has A-011218 DMA erratum */

		.trans_mode		= DSPI_XSPI_MODE,

		.max_clock_factor	= 8,

		.fifo_size		= 16,

		.regmap			= &dspi_regmap_config[DSPI_XSPI_REGMAP],

	},

	[LS1046A] = {

		/* Has A-011218 DMA erratum */

		.trans_mode		= DSPI_XSPI_MODE,

		.max_clock_factor	= 8,

		.fifo_size		= 16,

		.regmap			= &dspi_regmap_config[DSPI_XSPI_REGMAP],

	},

	[LS2080A] = {

		.trans_mode		= DSPI_XSPI_MODE,

		.max_clock_factor	= 8,

		.fifo_size		= 4,

		.regmap			= &dspi_regmap_config[DSPI_XSPI_REGMAP],

	},

	[LS2085A] = {

		.trans_mode		= DSPI_XSPI_MODE,

		.max_clock_factor	= 8,

		.fifo_size		= 4,

		.regmap			= &dspi_regmap_config[DSPI_XSPI_REGMAP],

	},

	[LX2160A] = {

		.trans_mode		= DSPI_XSPI_MODE,

		.max_clock_factor	= 8,

		.fifo_size		= 4,

		.regmap			= &dspi_regmap_config[DSPI_XSPI_REGMAP],

	},

	[MCF5441X] = {

		.trans_mode		= DSPI_DMA_MODE,

		.max_clock_factor	= 8,

		.fifo_size		= 16,

		.regmap			= &dspi_regmap_config[DSPI_REGMAP],

	},

	[S32G] = {

		.trans_mode	  = DSPI_XSPI_MODE,

		.max_clock_factor = 1,

		.fifo_size	  = 5,

		.regmap		  = &dspi_regmap_config[S32G_DSPI_XSPI_REGMAP],

	},

	[S32G_TARGET] = {

		.trans_mode	  = DSPI_DMA_MODE,

		.max_clock_factor = 1,

		.fifo_size	  = 5,

		.regmap		  = &dspi_regmap_config[S32G_DSPI_REGMAP],

	},

};
@@ -225,6 +350,7 @@ struct fsl_dspi { 
	const void				*tx;

	void					*rx;

	u16					tx_cmd;

	bool					mtf_enabled;

	const struct fsl_dspi_devtype_data	*devtype_data;



	struct completion			xfer_done;
@@ -247,6 +373,12 @@ struct fsl_dspi { 
	void (*dev_to_host)(struct fsl_dspi *dspi, u32 rxdata);

};



static bool is_s32g_dspi(struct fsl_dspi *data)

{

	return data->devtype_data == &devtype_data[S32G] ||

	       data->devtype_data == &devtype_data[S32G_TARGET];

}



static void dspi_native_host_to_dev(struct fsl_dspi *dspi, u32 *txdata)

{

	switch (dspi->oper_word_size) {
@@ -595,7 +727,7 @@ static void dspi_release_dma(struct fsl_dspi *dspi) 
}



static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,

			   unsigned long clkrate)

			   unsigned long clkrate, bool mtf_enabled)

{

	/* Valid baud rate pre-scaler values */

	int pbr_tbl[4] = {2, 3, 5, 7};
@@ -612,7 +744,13 @@ static void hz_to_spi_baud(char *pbr, char *br, int speed_hz, 


	for (i = 0; i < ARRAY_SIZE(brs); i++)

		for (j = 0; j < ARRAY_SIZE(pbr_tbl); j++) {

			if (mtf_enabled) {

				/* In MTF mode DBR=1 so frequency is doubled */

				scale = (brs[i] * pbr_tbl[j]) / 2;

			} else {

				scale = brs[i] * pbr_tbl[j];

			}



			if (scale >= scale_needed) {

				if (scale < minscale) {

					minscale = scale;
@@ -746,8 +884,12 @@ static void dspi_setup_accel(struct fsl_dspi *dspi) 
	struct spi_transfer *xfer = dspi->cur_transfer;

	bool odd = !!(dspi->len & 1);



	/* No accel for frames not multiple of 8 bits at the moment */

	if (xfer->bits_per_word % 8)

	/*

	 * No accel for DMA transfers or frames not multiples of 8 bits at the

	 * moment.

	 */

	if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE ||

	    xfer->bits_per_word % 8)

		goto no_accel;



	if (!odd && dspi->len <= dspi->devtype_data->fifo_size * 2) {
@@ -756,10 +898,7 @@ static void dspi_setup_accel(struct fsl_dspi *dspi) 
		dspi->oper_bits_per_word = 8;

	} else {

		/* Start off with maximum supported by hardware */

		if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)

		dspi->oper_bits_per_word = 32;

		else

			dspi->oper_bits_per_word = 16;



		/*

		 * And go down only if the buffer can't be sent with
@@ -1018,6 +1157,20 @@ static int dspi_transfer_one_message(struct spi_controller *ctlr, 
	return status;

}



static int dspi_set_mtf(struct fsl_dspi *dspi)

{

	if (spi_controller_is_target(dspi->ctlr))

		return 0;



	if (dspi->mtf_enabled)

		regmap_update_bits(dspi->regmap, SPI_MCR, SPI_MCR_MTFE,

				   SPI_MCR_MTFE);

	else

		regmap_update_bits(dspi->regmap, SPI_MCR, SPI_MCR_MTFE, 0);



	return 0;

}



static int dspi_setup(struct spi_device *spi)

{

	struct fsl_dspi *dspi = spi_controller_get_devdata(spi->controller);
@@ -1076,7 +1229,16 @@ static int dspi_setup(struct spi_device *spi) 
		cs_sck_delay, sck_cs_delay);



	clkrate = clk_get_rate(dspi->clk);

	hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate);



	if (is_s32g_dspi(dspi) && spi->max_speed_hz > SPI_25MHZ)

		dspi->mtf_enabled = true;

	else

		dspi->mtf_enabled = false;



	dspi_set_mtf(dspi);



	hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate,

		       dspi->mtf_enabled);



	/* Set PCS to SCK delay scale values */

	ns_delay_scale(&pcssck, &cssck, cs_sck_delay, clkrate);
@@ -1098,6 +1260,9 @@ static int dspi_setup(struct spi_device *spi) 
				  SPI_CTAR_PBR(pbr) |

				  SPI_CTAR_BR(br);



		if (dspi->mtf_enabled)

			chip->ctar_val |= SPI_CTAR_DBR;



		if (spi->mode & SPI_LSB_FIRST)

			chip->ctar_val |= SPI_CTAR_LSBFE;

	}
@@ -1151,112 +1316,14 @@ static const struct of_device_id fsl_dspi_dt_ids[] = { 
	}, {

		.compatible = "fsl,lx2160a-dspi",

		.data = &devtype_data[LX2160A],

	}, {

		.compatible = "nxp,s32g2-dspi",

		.data = &devtype_data[S32G],

	},

	{ /* sentinel */ }

};

MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids);



#ifdef CONFIG_PM_SLEEP

static int dspi_suspend(struct device *dev)

{

	struct fsl_dspi *dspi = dev_get_drvdata(dev);



	if (dspi->irq)

		disable_irq(dspi->irq);

	spi_controller_suspend(dspi->ctlr);

	clk_disable_unprepare(dspi->clk);



	pinctrl_pm_select_sleep_state(dev);



	return 0;

}



static int dspi_resume(struct device *dev)

{

	struct fsl_dspi *dspi = dev_get_drvdata(dev);

	int ret;



	pinctrl_pm_select_default_state(dev);



	ret = clk_prepare_enable(dspi->clk);

	if (ret)

		return ret;

	spi_controller_resume(dspi->ctlr);

	if (dspi->irq)

		enable_irq(dspi->irq);



	return 0;

}

#endif /* CONFIG_PM_SLEEP */



static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume);



static const struct regmap_range dspi_yes_ranges[] = {

	regmap_reg_range(SPI_MCR, SPI_MCR),

	regmap_reg_range(SPI_TCR, SPI_CTAR(3)),

	regmap_reg_range(SPI_SR, SPI_TXFR3),

	regmap_reg_range(SPI_RXFR0, SPI_RXFR3),

	regmap_reg_range(SPI_CTARE(0), SPI_CTARE(3)),

	regmap_reg_range(SPI_SREX, SPI_SREX),

};



static const struct regmap_access_table dspi_access_table = {

	.yes_ranges	= dspi_yes_ranges,

	.n_yes_ranges	= ARRAY_SIZE(dspi_yes_ranges),

};



static const struct regmap_range dspi_volatile_ranges[] = {

	regmap_reg_range(SPI_MCR, SPI_TCR),

	regmap_reg_range(SPI_SR, SPI_SR),

	regmap_reg_range(SPI_PUSHR, SPI_RXFR3),

};



static const struct regmap_access_table dspi_volatile_table = {

	.yes_ranges	= dspi_volatile_ranges,

	.n_yes_ranges	= ARRAY_SIZE(dspi_volatile_ranges),

};



static const struct regmap_config dspi_regmap_config = {

	.reg_bits	= 32,

	.val_bits	= 32,

	.reg_stride	= 4,

	.max_register	= 0x88,

	.volatile_table	= &dspi_volatile_table,

	.rd_table	= &dspi_access_table,

	.wr_table	= &dspi_access_table,

};



static const struct regmap_range dspi_xspi_volatile_ranges[] = {

	regmap_reg_range(SPI_MCR, SPI_TCR),

	regmap_reg_range(SPI_SR, SPI_SR),

	regmap_reg_range(SPI_PUSHR, SPI_RXFR3),

	regmap_reg_range(SPI_SREX, SPI_SREX),

};



static const struct regmap_access_table dspi_xspi_volatile_table = {

	.yes_ranges	= dspi_xspi_volatile_ranges,

	.n_yes_ranges	= ARRAY_SIZE(dspi_xspi_volatile_ranges),

};



static const struct regmap_config dspi_xspi_regmap_config[] = {

	{

		.reg_bits	= 32,

		.val_bits	= 32,

		.reg_stride	= 4,

		.max_register	= 0x13c,

		.volatile_table	= &dspi_xspi_volatile_table,

		.rd_table	= &dspi_access_table,

		.wr_table	= &dspi_access_table,

	},

	{

		.name		= "pushr",

		.reg_bits	= 16,

		.val_bits	= 16,

		.reg_stride	= 2,

		.max_register	= 0x2,

	},

};



static int dspi_init(struct fsl_dspi *dspi)

{

	unsigned int mcr;
@@ -1292,6 +1359,50 @@ static int dspi_init(struct fsl_dspi *dspi) 
	return 0;

}



#ifdef CONFIG_PM_SLEEP

static int dspi_suspend(struct device *dev)

{

	struct fsl_dspi *dspi = dev_get_drvdata(dev);



	if (dspi->irq)

		disable_irq(dspi->irq);

	spi_controller_suspend(dspi->ctlr);

	clk_disable_unprepare(dspi->clk);



	pinctrl_pm_select_sleep_state(dev);



	return 0;

}



static int dspi_resume(struct device *dev)

{

	struct fsl_dspi *dspi = dev_get_drvdata(dev);

	int ret;



	pinctrl_pm_select_default_state(dev);



	ret = clk_prepare_enable(dspi->clk);

	if (ret)

		return ret;

	spi_controller_resume(dspi->ctlr);



	ret = dspi_init(dspi);

	if (ret) {

		dev_err(dev, "failed to initialize dspi during resume\n");

		return ret;

	}



	dspi_set_mtf(dspi);



	if (dspi->irq)

		enable_irq(dspi->irq);



	return 0;

}

#endif /* CONFIG_PM_SLEEP */



static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume);



static int dspi_target_abort(struct spi_controller *host)

{

	struct fsl_dspi *dspi = spi_controller_get_devdata(host);
@@ -1316,7 +1427,6 @@ static int dspi_target_abort(struct spi_controller *host) 
static int dspi_probe(struct platform_device *pdev)

{

	struct device_node *np = pdev->dev.of_node;

	const struct regmap_config *regmap_config;

	struct fsl_dspi_platform_data *pdata;

	struct spi_controller *ctlr;

	int ret, cs_num, bus_num = -1;
@@ -1329,6 +1439,9 @@ static int dspi_probe(struct platform_device *pdev) 
	if (!dspi)

		return -ENOMEM;



	if (of_property_read_bool(np, "spi-slave"))

		ctlr = spi_alloc_target(&pdev->dev, 0);

	else

		ctlr = spi_alloc_host(&pdev->dev, 0);

	if (!ctlr)

		return -ENOMEM;
@@ -1368,9 +1481,6 @@ static int dspi_probe(struct platform_device *pdev) 
		of_property_read_u32(np, "bus-num", &bus_num);

		ctlr->bus_num = bus_num;



		if (of_property_read_bool(np, "spi-slave"))

			ctlr->target = true;



		dspi->devtype_data = of_device_get_match_data(&pdev->dev);

		if (!dspi->devtype_data) {

			dev_err(&pdev->dev, "can't get devtype_data\n");
@@ -1388,6 +1498,9 @@ static int dspi_probe(struct platform_device *pdev) 
		dspi->pushr_tx = 0;

	}



	if (spi_controller_is_target(ctlr) && is_s32g_dspi(dspi))

		dspi->devtype_data = &devtype_data[S32G_TARGET];



	if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)

		ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);

	else
@@ -1399,11 +1512,8 @@ static int dspi_probe(struct platform_device *pdev) 
		goto out_ctlr_put;

	}



	if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)

		regmap_config = &dspi_xspi_regmap_config[0];

	else

		regmap_config = &dspi_regmap_config;

	dspi->regmap = devm_regmap_init_mmio(&pdev->dev, base, regmap_config);

	dspi->regmap = devm_regmap_init_mmio(&pdev->dev, base,

					     dspi->devtype_data->regmap);

	if (IS_ERR(dspi->regmap)) {

		dev_err(&pdev->dev, "failed to init regmap: %ld\n",

				PTR_ERR(dspi->regmap));
@@ -1414,7 +1524,7 @@ static int dspi_probe(struct platform_device *pdev) 
	if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) {

		dspi->regmap_pushr = devm_regmap_init_mmio(

			&pdev->dev, base + SPI_PUSHR,

			&dspi_xspi_regmap_config[1]);

			&dspi_regmap_config[DSPI_PUSHR]);

		if (IS_ERR(dspi->regmap_pushr)) {

			dev_err(&pdev->dev,

				"failed to init pushr regmap: %ld\n",