Commit 3d751c56 authored by Will Deacon's avatar Will Deacon
Browse files

Merge branch 'for-next/cpufeature' into for-next/core 

* for-next/cpufeature:
  arm64: cpufeature: add Neoverse-V3AE to BBML2 allow list
  arm64: errata: Apply workarounds for Neoverse-V3AE
  arm64: cputype: Add Neoverse-V3AE definitions
  arm64: cpufeature: add AmpereOne to BBML2 allow list
  arm64: cpufeature: Add Olympus MIDR to BBML2 allow list
  arm64: cputype: Add NVIDIA Olympus definitions
  arm64: cputype: Remove duplicate Cortex-X1C definitions
  arm64: errata: Expand speculative SSBS workaround for Cortex-A720AE
  arm64: cputype: Add Cortex-A720AE definitions
  arm64/hwcap: Add hwcap for FEAT_LSFE
parents 5647d32f 8fca3852

Documentation/arch/arm64/elf_hwcaps.rst

+4 −0
Original line number Diff line number Diff line
@@ -441,6 +441,10 @@ HWCAP3_MTE_FAR 
HWCAP3_MTE_STORE_ONLY

    Functionality implied by ID_AA64PFR2_EL1.MTESTOREONLY == 0b0001.



HWCAP3_LSFE

    Functionality implied by ID_AA64ISAR3_EL1.LSFE == 0b0001





4. Unused AT_HWCAP bits

-----------------------

Documentation/arch/arm64/silicon-errata.rst

+2 −0
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@@ -200,6 +200,8 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-V3     | #3312417        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-V3AE   | #3312417        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | MMU-500         | #841119,826419  | ARM_SMMU_MMU_500_CPRE_ERRATA|

|                |                 | #562869,1047329 |                             |

+----------------+-----------------+-----------------+-----------------------------+

arch/arm64/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -1138,6 +1138,7 @@ config ARM64_ERRATUM_3194386 
	  * ARM Neoverse-V1 erratum 3324341

	  * ARM Neoverse V2 erratum 3324336

	  * ARM Neoverse-V3 erratum 3312417

	  * ARM Neoverse-V3AE erratum 3312417



	  On affected cores "MSR SSBS, #0" instructions may not affect

	  subsequent speculative instructions, which may permit unexepected

arch/arm64/include/asm/cputype.h

+6 −2
Original line number Diff line number Diff line
@@ -81,7 +81,6 @@ 
#define ARM_CPU_PART_CORTEX_A78AE	0xD42

#define ARM_CPU_PART_CORTEX_X1		0xD44

#define ARM_CPU_PART_CORTEX_A510	0xD46

#define ARM_CPU_PART_CORTEX_X1C		0xD4C

#define ARM_CPU_PART_CORTEX_A520	0xD80

#define ARM_CPU_PART_CORTEX_A710	0xD47

#define ARM_CPU_PART_CORTEX_A715	0xD4D
@@ -93,9 +92,11 @@ 
#define ARM_CPU_PART_NEOVERSE_V2	0xD4F

#define ARM_CPU_PART_CORTEX_A720	0xD81

#define ARM_CPU_PART_CORTEX_X4		0xD82

#define ARM_CPU_PART_NEOVERSE_V3AE	0xD83

#define ARM_CPU_PART_NEOVERSE_V3	0xD84

#define ARM_CPU_PART_CORTEX_X925	0xD85

#define ARM_CPU_PART_CORTEX_A725	0xD87

#define ARM_CPU_PART_CORTEX_A720AE	0xD89

#define ARM_CPU_PART_NEOVERSE_N3	0xD8E



#define APM_CPU_PART_XGENE		0x000
@@ -129,6 +130,7 @@ 


#define NVIDIA_CPU_PART_DENVER		0x003

#define NVIDIA_CPU_PART_CARMEL		0x004

#define NVIDIA_CPU_PART_OLYMPUS		0x010



#define FUJITSU_CPU_PART_A64FX		0x001
@@ -170,7 +172,6 @@ 
#define MIDR_CORTEX_A78AE	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78AE)

#define MIDR_CORTEX_X1	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1)

#define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510)

#define MIDR_CORTEX_X1C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1C)

#define MIDR_CORTEX_A520 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A520)

#define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710)

#define MIDR_CORTEX_A715 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A715)
@@ -182,9 +183,11 @@ 
#define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2)

#define MIDR_CORTEX_A720 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720)

#define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4)

#define MIDR_NEOVERSE_V3AE	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3AE)

#define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)

#define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)

#define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)

#define MIDR_CORTEX_A720AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720AE)

#define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3)

#define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)

#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
@@ -220,6 +223,7 @@ 


#define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER)

#define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)

#define MIDR_NVIDIA_OLYMPUS MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_OLYMPUS)

#define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX)

#define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)

#define MIDR_HISI_HIP09 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_HIP09)

arch/arm64/include/asm/hwcap.h

+1 −0
Original line number Diff line number Diff line
@@ -178,6 +178,7 @@ 
#define __khwcap3_feature(x)		(const_ilog2(HWCAP3_ ## x) + 128)

#define KERNEL_HWCAP_MTE_FAR		__khwcap3_feature(MTE_FAR)

#define KERNEL_HWCAP_MTE_STORE_ONLY	__khwcap3_feature(MTE_STORE_ONLY)

#define KERNEL_HWCAP_LSFE		__khwcap3_feature(LSFE)



/*

 * This yields a mask that user programs can use to figure out what