Commit 3d7de6e8 authored by William Wu's avatar William Wu Committed by Vinod Koul
Browse files

phy: rockchip: inno-usb2: Add usb2 phys support for rk3576 



The RK3576 SoC has two independent USB2.0 PHYs, and each PHY has
one port. This adds device specific data for it.

Signed-off-by: default avatarWilliam Wu <william.wu@rock-chips.com>
Signed-off-by: default avatarFrank Wang <frank.wang@rock-chips.com>
Reviewed-by: default avatarHeiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20241016073713.14133-4-frawang.cn@gmail.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 0217f4ae

drivers/phy/rockchip/phy-rockchip-inno-usb2.c

+103 −0
Original line number Diff line number Diff line
@@ -1510,6 +1510,30 @@ static int rk3128_usb2phy_tuning(struct rockchip_usb2phy *rphy) 
				BIT(2) << BIT_WRITEABLE_SHIFT | 0);

}



static int rk3576_usb2phy_tuning(struct rockchip_usb2phy *rphy)

{

	int ret;

	u32 reg = rphy->phy_cfg->reg;



	/* Deassert SIDDQ to power on analog block */

	ret = regmap_write(rphy->grf, reg + 0x0010, GENMASK(29, 29) | 0x0000);

	if (ret)

		return ret;



	/* Do reset after exit IDDQ mode */

	ret = rockchip_usb2phy_reset(rphy);

	if (ret)

		return ret;



	/* HS DC Voltage Level Adjustment 4'b1001 : +5.89% */

	ret |= regmap_write(rphy->grf, reg + 0x000c, GENMASK(27, 24) | 0x0900);



	/* HS Transmitter Pre-Emphasis Current Control 2'b10 : 2x */

	ret |= regmap_write(rphy->grf, reg + 0x0010, GENMASK(20, 19) | 0x0010);



	return ret;

}



static int rk3588_usb2phy_tuning(struct rockchip_usb2phy *rphy)

{

	int ret;
@@ -1938,6 +1962,84 @@ static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = { 
	{ /* sentinel */ }

};



static const struct rockchip_usb2phy_cfg rk3576_phy_cfgs[] = {

	{

		.reg = 0x0,

		.num_ports	= 1,

		.phy_tuning	= rk3576_usb2phy_tuning,

		.clkout_ctl	= { 0x0008, 0, 0, 1, 0 },

		.port_cfgs	= {

			[USB2PHY_PORT_OTG] = {

				.phy_sus	= { 0x0000, 8, 0, 0, 0x1d1 },

				.bvalid_det_en	= { 0x00c0, 1, 1, 0, 1 },

				.bvalid_det_st	= { 0x00c4, 1, 1, 0, 1 },

				.bvalid_det_clr = { 0x00c8, 1, 1, 0, 1 },

				.ls_det_en	= { 0x00c0, 0, 0, 0, 1 },

				.ls_det_st	= { 0x00c4, 0, 0, 0, 1 },

				.ls_det_clr	= { 0x00c8, 0, 0, 0, 1 },

				.disfall_en	= { 0x00c0, 6, 6, 0, 1 },

				.disfall_st	= { 0x00c4, 6, 6, 0, 1 },

				.disfall_clr	= { 0x00c8, 6, 6, 0, 1 },

				.disrise_en	= { 0x00c0, 5, 5, 0, 1 },

				.disrise_st	= { 0x00c4, 5, 5, 0, 1 },

				.disrise_clr	= { 0x00c8, 5, 5, 0, 1 },

				.utmi_avalid	= { 0x0080, 1, 1, 0, 1 },

				.utmi_bvalid	= { 0x0080, 0, 0, 0, 1 },

				.utmi_ls	= { 0x0080, 5, 4, 0, 1 },

			}

		},

		.chg_det = {

			.cp_det		= { 0x0080, 8, 8, 0, 1 },

			.dcp_det	= { 0x0080, 8, 8, 0, 1 },

			.dp_det		= { 0x0080, 9, 9, 1, 0 },

			.idm_sink_en	= { 0x0010, 5, 5, 1, 0 },

			.idp_sink_en	= { 0x0010, 5, 5, 0, 1 },

			.idp_src_en	= { 0x0010, 14, 14, 0, 1 },

			.rdm_pdwn_en	= { 0x0010, 14, 14, 0, 1 },

			.vdm_src_en	= { 0x0010, 7, 6, 0, 3 },

			.vdp_src_en	= { 0x0010, 7, 6, 0, 3 },

		},

	},

	{

		.reg = 0x2000,

		.num_ports	= 1,

		.phy_tuning	= rk3576_usb2phy_tuning,

		.clkout_ctl	= { 0x2008, 0, 0, 1, 0 },

		.port_cfgs	= {

			[USB2PHY_PORT_OTG] = {

				.phy_sus	= { 0x2000, 8, 0, 0, 0x1d1 },

				.bvalid_det_en	= { 0x20c0, 1, 1, 0, 1 },

				.bvalid_det_st	= { 0x20c4, 1, 1, 0, 1 },

				.bvalid_det_clr = { 0x20c8, 1, 1, 0, 1 },

				.ls_det_en	= { 0x20c0, 0, 0, 0, 1 },

				.ls_det_st	= { 0x20c4, 0, 0, 0, 1 },

				.ls_det_clr	= { 0x20c8, 0, 0, 0, 1 },

				.disfall_en	= { 0x20c0, 6, 6, 0, 1 },

				.disfall_st	= { 0x20c4, 6, 6, 0, 1 },

				.disfall_clr	= { 0x20c8, 6, 6, 0, 1 },

				.disrise_en	= { 0x20c0, 5, 5, 0, 1 },

				.disrise_st	= { 0x20c4, 5, 5, 0, 1 },

				.disrise_clr	= { 0x20c8, 5, 5, 0, 1 },

				.utmi_avalid	= { 0x2080, 1, 1, 0, 1 },

				.utmi_bvalid	= { 0x2080, 0, 0, 0, 1 },

				.utmi_ls	= { 0x2080, 5, 4, 0, 1 },

			}

		},

		.chg_det = {

			.cp_det		= { 0x2080, 8, 8, 0, 1 },

			.dcp_det	= { 0x2080, 8, 8, 0, 1 },

			.dp_det		= { 0x2080, 9, 9, 1, 0 },

			.idm_sink_en	= { 0x2010, 5, 5, 1, 0 },

			.idp_sink_en	= { 0x2010, 5, 5, 0, 1 },

			.idp_src_en	= { 0x2010, 14, 14, 0, 1 },

			.rdm_pdwn_en	= { 0x2010, 14, 14, 0, 1 },

			.vdm_src_en	= { 0x2010, 7, 6, 0, 3 },

			.vdp_src_en	= { 0x2010, 7, 6, 0, 3 },

		},

	},

	{ /* sentinel */ }

};



static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = {

	{

		.reg = 0x0000,
@@ -2109,6 +2211,7 @@ static const struct of_device_id rockchip_usb2phy_dt_match[] = { 
	{ .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },

	{ .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },

	{ .compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs },

	{ .compatible = "rockchip,rk3576-usb2phy", .data = &rk3576_phy_cfgs },

	{ .compatible = "rockchip,rk3588-usb2phy", .data = &rk3588_phy_cfgs },

	{ .compatible = "rockchip,rv1108-usb2phy", .data = &rv1108_phy_cfgs },

	{}