Commit 3e057e05 authored by Martin Botka's avatar Martin Botka Committed by Viresh Kumar
Browse files

arm64: dts: allwinner: h616: Add CPU OPPs table 



Add an Operating Performance Points table for the CPU cores to enable
Dynamic Voltage & Frequency Scaling (DVFS) on the H616.
The values were taken from the BSP sources. There is a separate OPP set
seen on some H700 devices, but they didn't really work out in testing, so
they are not included for now.

Also add the needed cpu_speed_grade nvmem cell and the cooling cells
properties, to enable passive cooling.

Signed-off-by: default avatarMartin Botka <martin.botka@somainline.org>
[Andre: rework to minimise opp-microvolt properties]
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
Acked-by: default avatarJernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
parent e2e2dcd2

arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi

0 → 100644
+115 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

// Copyright (C) 2023 Martin Botka <martin@somainline.org>



/ {

	cpu_opp_table: opp-table-cpu {

		compatible = "allwinner,sun50i-h616-operating-points";

		nvmem-cells = <&cpu_speed_grade>;

		opp-shared;



		opp-480000000 {

			opp-hz = /bits/ 64 <480000000>;

			opp-microvolt = <900000>;

			clock-latency-ns = <244144>; /* 8 32k periods */

			opp-supported-hw = <0x1f>;

		};



		opp-600000000 {

			opp-hz = /bits/ 64 <600000000>;

			opp-microvolt = <900000>;

			clock-latency-ns = <244144>; /* 8 32k periods */

			opp-supported-hw = <0x12>;

		};



		opp-720000000 {

			opp-hz = /bits/ 64 <720000000>;

			opp-microvolt = <900000>;

			clock-latency-ns = <244144>; /* 8 32k periods */

			opp-supported-hw = <0x0d>;

		};



		opp-792000000 {

			opp-hz = /bits/ 64 <792000000>;

			opp-microvolt-speed1 = <900000>;

			opp-microvolt-speed4 = <940000>;

			clock-latency-ns = <244144>; /* 8 32k periods */

			opp-supported-hw = <0x12>;

		};



		opp-936000000 {

			opp-hz = /bits/ 64 <936000000>;

			opp-microvolt = <900000>;

			clock-latency-ns = <244144>; /* 8 32k periods */

			opp-supported-hw = <0x0d>;

		};



		opp-1008000000 {

			opp-hz = /bits/ 64 <1008000000>;

			opp-microvolt-speed0 = <950000>;

			opp-microvolt-speed1 = <940000>;

			opp-microvolt-speed2 = <950000>;

			opp-microvolt-speed3 = <950000>;

			opp-microvolt-speed4 = <1020000>;

			clock-latency-ns = <244144>; /* 8 32k periods */

			opp-supported-hw = <0x1f>;

		};



		opp-1104000000 {

			opp-hz = /bits/ 64 <1104000000>;

			opp-microvolt-speed0 = <1000000>;

			opp-microvolt-speed2 = <1000000>;

			opp-microvolt-speed3 = <1000000>;

			clock-latency-ns = <244144>; /* 8 32k periods */

			opp-supported-hw = <0x0d>;

		};



		opp-1200000000 {

			opp-hz = /bits/ 64 <1200000000>;

			opp-microvolt-speed0 = <1050000>;

			opp-microvolt-speed1 = <1020000>;

			opp-microvolt-speed2 = <1050000>;

			opp-microvolt-speed3 = <1050000>;

			opp-microvolt-speed4 = <1100000>;

			clock-latency-ns = <244144>; /* 8 32k periods */

			opp-supported-hw = <0x1f>;

		};



		opp-1320000000 {

			opp-hz = /bits/ 64 <1320000000>;

			opp-microvolt = <1100000>;

			clock-latency-ns = <244144>; /* 8 32k periods */

			opp-supported-hw = <0x1d>;

		};



		opp-1416000000 {

			opp-hz = /bits/ 64 <1416000000>;

			opp-microvolt = <1100000>;

			clock-latency-ns = <244144>; /* 8 32k periods */

			opp-supported-hw = <0x0d>;

		};



		opp-1512000000 {

			opp-hz = /bits/ 64 <1512000000>;

			opp-microvolt-speed1 = <1100000>;

			opp-microvolt-speed3 = <1100000>;

			clock-latency-ns = <244144>; /* 8 32k periods */

			opp-supported-hw = <0x0a>;

		};

	};

};



&cpu0 {

	operating-points-v2 = <&cpu_opp_table>;

};



&cpu1 {

	operating-points-v2 = <&cpu_opp_table>;

};



&cpu2 {

	operating-points-v2 = <&cpu_opp_table>;

};



&cpu3 {

	operating-points-v2 = <&cpu_opp_table>;

};

arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ cpu0: cpu@0 { 
			reg = <0>;

			enable-method = "psci";

			clocks = <&ccu CLK_CPUX>;

			#cooling-cells = <2>;

		};



		cpu1: cpu@1 {
@@ -34,6 +35,7 @@ cpu1: cpu@1 { 
			reg = <1>;

			enable-method = "psci";

			clocks = <&ccu CLK_CPUX>;

			#cooling-cells = <2>;

		};



		cpu2: cpu@2 {
@@ -42,6 +44,7 @@ cpu2: cpu@2 { 
			reg = <2>;

			enable-method = "psci";

			clocks = <&ccu CLK_CPUX>;

			#cooling-cells = <2>;

		};



		cpu3: cpu@3 {
@@ -50,6 +53,7 @@ cpu3: cpu@3 { 
			reg = <3>;

			enable-method = "psci";

			clocks = <&ccu CLK_CPUX>;

			#cooling-cells = <2>;

		};

	};
@@ -156,6 +160,10 @@ sid: efuse@3006000 { 
			ths_calibration: thermal-sensor-calibration@14 {

				reg = <0x14 0x8>;

			};



			cpu_speed_grade: cpu-speed-grade@0 {

				reg = <0x0 2>;

			};

		};



		watchdog: watchdog@30090a0 {