Commit 3e256d4c authored by Jai Luthra's avatar Jai Luthra Committed by Conor Dooley
Browse files

riscv: dts: starfive: jh7110: Drop CAMSS node 



The starfive-camss driver and bindings were dropped, as they were no
longer being worked upon for destaging.

Drop the relevant node as well to avoid the following build warning:
"failed to match any schema with compatible: ['starfive,jh7110-camss']"

Reported-by: default avatarConor Dooley <conor@kernel.org>
Closes: https://lore.kernel.org/all/20260420-very-cartel-645595ffd1c7@spud/


Signed-off-by: default avatarJai Luthra <jai.luthra@ideasonboard.com>
Reviewed-by: default avatarChanghuang Liang <changhuang.liang@starfivetech.com>
Reviewed-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
parent 254f4963

arch/riscv/boot/dts/starfive/jh7110-common.dtsi

+1 −26
Original line number Diff line number Diff line
@@ -135,29 +135,6 @@ &tdm_ext { 
	clock-frequency = <49152000>;

};



&camss {

	assigned-clocks = <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>,

			  <&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>;

	assigned-clock-rates = <49500000>, <198000000>;



	ports {

		#address-cells = <1>;

		#size-cells = <0>;



		port@0 {

			reg = <0>;

		};



		port@1 {

			reg = <1>;



			camss_from_csi2rx: endpoint {

				remote-endpoint = <&csi2rx_to_camss>;

			};

		};

	};

};



&csi2rx {

	assigned-clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>;

	assigned-clock-rates = <297000000>;
@@ -175,9 +152,7 @@ port@0 { 
		port@1 {

			reg = <1>;



			csi2rx_to_camss: endpoint {

				remote-endpoint = <&camss_from_csi2rx>;

			};

			/* remote CAMSS endpoint */

		};

	};

};

arch/riscv/boot/dts/starfive/jh7110.dtsi

+0 −28
Original line number Diff line number Diff line
@@ -1199,34 +1199,6 @@ csi_phy: phy@19820000 { 
			#phy-cells = <0>;

		};



		camss: isp@19840000 {

			compatible = "starfive,jh7110-camss";

			reg = <0x0 0x19840000 0x0 0x10000>,

			      <0x0 0x19870000 0x0 0x30000>;

			reg-names = "syscon", "isp";

			clocks = <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>,

				 <&ispcrg JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C>,

				 <&ispcrg JH7110_ISPCLK_DVP_INV>,

				 <&ispcrg JH7110_ISPCLK_VIN_P_AXI_WR>,

				 <&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>,

				 <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>,

				 <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>;

			clock-names = "apb_func", "wrapper_clk_c", "dvp_inv",

				      "axiwr", "mipi_rx0_pxl", "ispcore_2x",

				      "isp_axi";

			resets = <&ispcrg JH7110_ISPRST_ISPV2_TOP_WRAPPER_P>,

				 <&ispcrg JH7110_ISPRST_ISPV2_TOP_WRAPPER_C>,

				 <&ispcrg JH7110_ISPRST_VIN_P_AXI_RD>,

				 <&ispcrg JH7110_ISPRST_VIN_P_AXI_WR>,

				 <&syscrg JH7110_SYSRST_ISP_TOP>,

				 <&syscrg JH7110_SYSRST_ISP_TOP_AXI>;

			reset-names = "wrapper_p", "wrapper_c", "axird",

				      "axiwr", "isp_top_n", "isp_top_axi";

			power-domains = <&pwrc JH7110_PD_ISP>;

			interrupts = <92>, <87>, <90>, <88>;

			status = "disabled";

		};



		voutcrg: clock-controller@295c0000 {

			compatible = "starfive,jh7110-voutcrg";

			reg = <0x0 0x295c0000 0x0 0x10000>;