Commit 3e422caa authored by Robert Richter's avatar Robert Richter Committed by Dave Jiang
Browse files

cxl: Simplify cxl_root_ops allocation and handling 



A root port's callback handlers are collected in struct cxl_root_ops.
The structure is dynamically allocated, though it contains only a
single pointer in it. This also requires to check two pointers to
check for the existance of a callback.

Simplify the allocation, release and handler check by embedding the
ops statically in struct cxl_root.

Reviewed-by: default avatarDave Jiang <dave.jiang@intel.com>
Reviewed-by: default avatarJonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: default avatarAlison Schofield <alison.schofield@intel.com>
Signed-off-by: default avatarRobert Richter <rrichter@amd.com>
Link: https://patch.msgid.link/20260114164837.1076338-5-rrichter@amd.com


Signed-off-by: default avatarDave Jiang <dave.jiang@intel.com>
parent 98ceb1a4

drivers/cxl/acpi.c

+2 −5
Original line number Diff line number Diff line
@@ -318,10 +318,6 @@ static int cxl_acpi_qos_class(struct cxl_root *cxl_root, 
	return cxl_acpi_evaluate_qtg_dsm(handle, coord, entries, qos_class);

}



static const struct cxl_root_ops acpi_root_ops = {

	.qos_class = cxl_acpi_qos_class,

};



static void del_cxl_resource(struct resource *res)

{

	if (!res)
@@ -923,9 +919,10 @@ static int cxl_acpi_probe(struct platform_device *pdev) 
	cxl_res->end = -1;

	cxl_res->flags = IORESOURCE_MEM;



	cxl_root = devm_cxl_add_root(host, &acpi_root_ops);

	cxl_root = devm_cxl_add_root(host);

	if (IS_ERR(cxl_root))

		return PTR_ERR(cxl_root);

	cxl_root->ops.qos_class = cxl_acpi_qos_class;

	root_port = &cxl_root->port;



	rc = bus_for_each_dev(adev->dev.bus, NULL, root_port,

drivers/cxl/core/cdat.c

+4 −4
Original line number Diff line number Diff line
@@ -213,7 +213,7 @@ static int cxl_port_perf_data_calculate(struct cxl_port *port, 
	if (!cxl_root)

		return -ENODEV;



	if (!cxl_root->ops || !cxl_root->ops->qos_class)

	if (!cxl_root->ops.qos_class)

		return -EOPNOTSUPP;



	xa_for_each(dsmas_xa, index, dent) {
@@ -221,7 +221,7 @@ static int cxl_port_perf_data_calculate(struct cxl_port *port, 


		cxl_coordinates_combine(dent->coord, dent->cdat_coord, ep_c);

		dent->entries = 1;

		rc = cxl_root->ops->qos_class(cxl_root,

		rc = cxl_root->ops.qos_class(cxl_root,

					     &dent->coord[ACCESS_COORDINATE_CPU],

					     1, &qos_class);

		if (rc != 1)

drivers/cxl/core/port.c

+2 −6
Original line number Diff line number Diff line
@@ -954,19 +954,15 @@ struct cxl_port *devm_cxl_add_port(struct device *host, 
}

EXPORT_SYMBOL_NS_GPL(devm_cxl_add_port, "CXL");



struct cxl_root *devm_cxl_add_root(struct device *host,

				   const struct cxl_root_ops *ops)

struct cxl_root *devm_cxl_add_root(struct device *host)

{

	struct cxl_root *cxl_root;

	struct cxl_port *port;



	port = devm_cxl_add_port(host, host, CXL_RESOURCE_NONE, NULL);

	if (IS_ERR(port))

		return ERR_CAST(port);



	cxl_root = to_cxl_root(port);

	cxl_root->ops = ops;

	return cxl_root;

	return to_cxl_root(port);

}

EXPORT_SYMBOL_NS_GPL(devm_cxl_add_root, "CXL");

drivers/cxl/cxl.h

+10 −9
Original line number Diff line number Diff line
@@ -646,6 +646,14 @@ struct cxl_port { 
	resource_size_t component_reg_phys;

};



struct cxl_root;



struct cxl_root_ops {

	int (*qos_class)(struct cxl_root *cxl_root,

			 struct access_coordinate *coord, int entries,

			 int *qos_class);

};



/**

 * struct cxl_root - logical collection of root cxl_port items

 *
@@ -654,7 +662,7 @@ struct cxl_port { 
 */

struct cxl_root {

	struct cxl_port port;

	const struct cxl_root_ops *ops;

	struct cxl_root_ops ops;

};



static inline struct cxl_root *
@@ -663,12 +671,6 @@ to_cxl_root(const struct cxl_port *port) 
	return container_of(port, struct cxl_root, port);

}



struct cxl_root_ops {

	int (*qos_class)(struct cxl_root *cxl_root,

			 struct access_coordinate *coord, int entries,

			 int *qos_class);

};



static inline struct cxl_dport *

cxl_find_dport_by_dev(struct cxl_port *port, const struct device *dport_dev)

{
@@ -782,8 +784,7 @@ struct cxl_port *devm_cxl_add_port(struct device *host, 
				   struct device *uport_dev,

				   resource_size_t component_reg_phys,

				   struct cxl_dport *parent_dport);

struct cxl_root *devm_cxl_add_root(struct device *host,

				   const struct cxl_root_ops *ops);

struct cxl_root *devm_cxl_add_root(struct device *host);

struct cxl_root *find_cxl_root(struct cxl_port *port);



DEFINE_FREE(put_cxl_root, struct cxl_root *, if (_T) put_device(&_T->port.dev))