Commit 3e47bcc9 authored by Sean Anderson's avatar Sean Anderson Committed by Bjorn Helgaas
Browse files

dt-bindings: pci: xilinx-nwl: Add phys property 

Add phys properties so Linux can power-on/configure the GTR transceivers
(xlnx,zynqmp-psgtr-v1.1).

Link: https://lore.kernel.org/r/20240531161337.864994-2-sean.anderson@linux.dev


Signed-off-by: default avatarSean Anderson <sean.anderson@linux.dev>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: default avatarRob Herring (Arm) <robh@kernel.org>
parent cfd67903

Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml

+7 −0
Original line number Diff line number Diff line
@@ -61,6 +61,11 @@ properties: 
  interrupt-map:

    maxItems: 4



  phys:

    minItems: 1

    maxItems: 4

    description: One phy per logical lane, in order



  power-domains:

    maxItems: 1
@@ -110,6 +115,7 @@ examples: 
  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/interrupt-controller/irq.h>

    #include <dt-bindings/phy/phy.h>

    #include <dt-bindings/power/xlnx-zynqmp-power.h>

    soc {

        #address-cells = <2>;
@@ -138,6 +144,7 @@ examples: 
                            <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,

                            <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;

            msi-parent = <&nwl_pcie>;

            phys = <&psgtr 0 PHY_TYPE_PCIE 0 0>;

            power-domains = <&zynqmp_firmware PD_PCIE>;

            iommus = <&smmu 0x4d0>;

            pcie_intc: legacy-interrupt-controller {