Commit 3e5be4e1 authored Dec 11, 2024 by Anshuman Khandual Committed by Will Deacon Dec 19, 2024

docs: arm64: Document EL3 requirements for cpu debug architecture



This documents EL3 requirements for debug architecture. The register field
MDCR_EL3.TDA needs to be cleared for accesses into debug registers without
any trap being generated into EL3. CPU debug registers like DBGBCR<n>_EL1,
DBGBVR<n>_EL1, DBGWCR<n>_EL1, DBGWVR<n>_EL1 and MDSCR_EL1 are already being
accessed for HW breakpoint, watchpoint and debug monitor implementations on
the platform.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Jonathan Corbet <corbet@lwn.net>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-doc@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Link: https://lore.kernel.org/r/20241211065425.1106683-2-anshuman.khandual@arm.com


Signed-off-by: Will Deacon <will@kernel.org>

parent fac04efc

Documentation/arch/arm64/booting.rst

+6 −0

Original line number	Diff line number	Diff line
		@@ -449,6 +449,12 @@ Before jumping into the kernel, the following conditions must be met:

		- HFGWTR_EL2.nGCS_EL0 (bit 52) must be initialised to 0b1.

		- For CPUs with debug architecture i.e FEAT_Debugv8pN (all versions):

		- If EL3 is present:

		- MDCR_EL3.TDA (bit 9) must be initialized to 0b0

		The requirements described above for CPU mode, caches, MMUs, architected
		timers, coherency and system registers apply to all CPUs. All CPUs must
		enter the kernel in the same exception level. Where the values documented