Commit 3e65e426 authored by Fabio Estevam's avatar Fabio Estevam Committed by Heiko Stuebner
Browse files

clk: rockchip: Add clock controller for the RV1103B 



Add the clock and reset tree definitions for the RV1103B SoC.

Based on the 5.10 Rockchip vendor kernel driver.

Signed-off-by: default avatarFabio Estevam <festevam@nabladev.com>
Link: https://patch.msgid.link/20260210022620.172570-2-festevam@gmail.com


Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 75d627e5

drivers/clk/rockchip/Kconfig

+7 −0
Original line number Diff line number Diff line
@@ -16,6 +16,13 @@ config CLK_PX30 
	help

	  Build the driver for PX30 Clock Driver.



config CLK_RV1103B

	bool "Rockchip RV1103B clock controller support"

	depends on ARM || COMPILE_TEST

	default y

	help

	  Build the driver for RV1103B Clock Driver.



config CLK_RV110X

	bool "Rockchip RV110x clock controller support"

	depends on ARM || COMPILE_TEST

drivers/clk/rockchip/Makefile

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@@ -18,6 +18,7 @@ clk-rockchip-y += gate-link.o 
clk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o



obj-$(CONFIG_CLK_PX30)          += clk-px30.o

obj-$(CONFIG_CLK_RV1103B)	+= clk-rv1103b.o

obj-$(CONFIG_CLK_RV110X)        += clk-rv1108.o

obj-$(CONFIG_CLK_RV1126)        += clk-rv1126.o

obj-$(CONFIG_CLK_RV1126B)	+= clk-rv1126b.o rst-rv1126b.o

drivers/clk/rockchip/clk-rv1103b.c

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+658 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/clk/rockchip/clk.h

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@@ -66,6 +66,55 @@ struct clk; 
#define PX30_PMU_CLKGATE_CON(x)		((x) * 0x4 + 0x80)

#define PX30_PMU_MODE			0x0020



#define RV1103B_TOPCRU_BASE		0x60000

#define RV1103B_PERICRU_BASE		0x0

#define RV1103B_VICRU_BASE		0x30000

#define RV1103B_NPUCRU_BASE		0x20000

#define RV1103B_CORECRU_BASE		0x40000

#define RV1103B_VEPUCRU_BASE		0x10000

#define RV1103B_DDRCRU_BASE		0x50000

#define RV1103B_SUBDDRCRU_BASE		0x58000

#define RV1103B_PMUCRU_BASE		0x70000

#define RV1103B_PMU1CRU_BASE		0x80000



#define RV1103B_PMUCLKSEL_CON(x)	((x) * 0x4 + 0x300 + RV1103B_PMUCRU_BASE)

#define RV1103B_PMUCLKGATE_CON(x)	((x) * 0x4 + 0x800 + RV1103B_PMUCRU_BASE)

#define RV1103B_PMUSOFTRST_CON(x)	((x) * 0x4 + 0xa00 + RV1103B_PMUCRU_BASE)

#define RV1103B_PMU1CLKSEL_CON(x)	((x) * 0x4 + 0x300 + RV1103B_PMU1CRU_BASE)

#define RV1103B_PMU1CLKGATE_CON(x)	((x) * 0x4 + 0x800 + RV1103B_PMU1CRU_BASE)

#define RV1103B_PMU1SOFTRST_CON(x)	((x) * 0x4 + 0xa00 + RV1103B_PMU1CRU_BASE)

#define RV1103B_PLL_CON(x)		((x) * 0x4 + RV1103B_TOPCRU_BASE)

#define RV1103B_MODE_CON		(0x280 + RV1103B_TOPCRU_BASE)

#define RV1103B_CLKSEL_CON(x)		((x) * 0x4 + 0x300 + RV1103B_TOPCRU_BASE)

#define RV1103B_CLKGATE_CON(x)		((x) * 0x4 + 0x800 + RV1103B_TOPCRU_BASE)

#define RV1103B_SOFTRST_CON(x)		((x) * 0x4 + 0xa00 + RV1103B_TOPCRU_BASE)

#define RV1103B_GLB_SRST_FST		(0xc08 + RV1103B_TOPCRU_BASE)

#define RV1103B_GLB_SRST_SND		(0xc0c + RV1103B_TOPCRU_BASE)

#define RV1103B_CLK_SAI_FRAC_DIV_HIGH	(0xcc0 + RV1103B_TOPCRU_BASE)

#define RV1103B_PERICLKSEL_CON(x)	((x) * 0x4 + 0x300 + RV1103B_PERICRU_BASE)

#define RV1103B_PERICLKGATE_CON(x)	((x) * 0x4 + 0x800 + RV1103B_PERICRU_BASE)

#define RV1103B_PERISOFTRST_CON(x)	((x) * 0x4 + 0xa00 + RV1103B_PERICRU_BASE)

#define RV1103B_PERICRU_IP_CON		(0xc08 + RV1103B_PERICRU_BASE)

#define RV1103B_VICLKSEL_CON(x)		((x) * 0x4 + 0x300 + RV1103B_VICRU_BASE)

#define RV1103B_VICLKGATE_CON(x)	((x) * 0x4 + 0x800 + RV1103B_VICRU_BASE)

#define RV1103B_VISOFTRST_CON(x)	((x) * 0x4 + 0xa00 + RV1103B_VICRU_BASE)

#define RV1103B_NPUCLKSEL_CON(x)	((x) * 0x4 + 0x300 + RV1103B_NPUCRU_BASE)

#define RV1103B_NPUCLKGATE_CON(x)	((x) * 0x4 + 0x800 + RV1103B_NPUCRU_BASE)

#define RV1103B_NPUSOFTRST_CON(x)	((x) * 0x4 + 0xa00 + RV1103B_NPUCRU_BASE)

#define RV1103B_CORECLKSEL_CON(x)	((x) * 0x4 + 0x300 + RV1103B_CORECRU_BASE)

#define RV1103B_CORECLKGATE_CON(x)	((x) * 0x4 + 0x800 + RV1103B_CORECRU_BASE)

#define RV1103B_CORESOFTRST_CON(x)	((x) * 0x4 + 0xa00 + RV1103B_CORECRU_BASE)

#define RV1103B_VEPUCLKSEL_CON(x)	((x) * 0x4 + 0x300 + RV1103B_VEPUCRU_BASE)

#define RV1103B_VEPUCLKGATE_CON(x)	((x) * 0x4 + 0x800 + RV1103B_VEPUCRU_BASE)

#define RV1103B_VEPUSOFTRST_CON(x)	((x) * 0x4 + 0xa00 + RV1103B_VEPUCRU_BASE)

#define RV1103B_DDRCLKSEL_CON(x)	((x) * 0x4 + 0x300 + RV1103B_DDRCRU_BASE)

#define RV1103B_DDRCLKGATE_CON(x)	((x) * 0x4 + 0x800 + RV1103B_DDRCRU_BASE)

#define RV1103B_DDRSOFTRST_CON(x)	((x) * 0x4 + 0xa00 + RV1103B_DDRCRU_BASE)

#define RV1103B_SUBDDRCLKSEL_CON(x)	((x) * 0x4 + 0x300 + RV1103B_SUBDDRCRU_BASE)

#define RV1103B_SUBDDRCLKGATE_CON(x)	((x) * 0x4 + 0x800 + RV1103B_SUBDDRCRU_BASE)

#define RV1103B_SUBDDRSOFTRST_CON(x)	((x) * 0x4 + 0xa00 + RV1103B_SUBDDRCRU_BASE)

#define RV1103B_SUBDDRMODE_CON		(0x280 + RV1103B_SUBDDRCRU_BASE)



#define RV1108_PLL_CON(x)		((x) * 0x4)

#define RV1108_CLKSEL_CON(x)		((x) * 0x4 + 0x60)

#define RV1108_CLKGATE_CON(x)		((x) * 0x4 + 0x120)