Commit 3e6b0227 authored by Marco Felsch's avatar Marco Felsch Committed by Abel Vesa
Browse files

clk: imx: fracn-gppll: Add 241.90 MHz Support 



Some parallel panels have a pixelclk of 24.19 MHz. Add support for
241.90 MHz so a by 10 divider can be used to derive the exact pixelclk.

Signed-off-by: default avatarMarco Felsch <m.felsch@pengutronix.de>
Reviewed-by: default avatarAbel Vesa <abel.vesa@oss.qualcomm.com>
Reviewed-by: default avatarPeng Fan <peng.fan@nxp.com>
Acked-by: default avatarDaniel Baluta <daniel.baluta@nxp.com>
Link: https://patch.msgid.link/20260113-v6-18-topic-clk-fracn-gppll-v3-2-45da70f43c98@pengutronix.de


Signed-off-by: default avatarAbel Vesa <abel.vesa@oss.qualcomm.com>
parent 9bb910b0

drivers/clk/imx/clk-fracn-gppll.c

+2 −1
Original line number Diff line number Diff line
@@ -89,7 +89,8 @@ static const struct imx_fracn_gppll_rate_table fracn_tbl[] = { 
	PLL_FRACN_GP(400000000U, 200, 0, 1, 0, 12),

	PLL_FRACN_GP(393216000U, 163, 84, 100, 0, 10),

	PLL_FRACN_GP(332600000U, 138, 584, 1000, 0, 10),

	PLL_FRACN_GP(300000000U, 150, 0, 1, 0, 12)

	PLL_FRACN_GP(300000000U, 150, 0, 1, 0, 12),

	PLL_FRACN_GP(241900000U, 201, 584, 1000, 0, 20),

};



struct imx_fracn_gppll_clk imx_fracn_gppll = {