Commit 3e76237e authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'v6.9-rockchip-clk1' of... 

Merge tag 'v6.9-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip

Pull Rockchip clk driver updates from Heiko Stuebner:

 - New pll-rate for rk3568
 - i2s rate improvements for rk3399
 - rk3588 syscon clock fixes and removal of overall clock-number from
   the rk3588 binding header
 - a prerequisite for later improvements to the rk3588 linked clocks

* tag 'v6.9-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: rk3399: Allow to set rate of clk_i2s0_frac's parent
  clk: rockchip: rk3588: use linked clock ID for GATE_LINK
  clk: rockchip: rk3588: fix indent
  clk: rockchip: rk3588: fix pclk_vo0grf and pclk_vo1grf
  dt-bindings: clock: rk3588: add missing PCLK_VO1GRF
  dt-bindings: clock: rk3588: drop CLK_NR_CLKS
  clk: rockchip: rk3588: fix CLK_NR_CLKS usage
  clk: rockchip: rk3568: Add PLL rate for 128MHz
parents 6613476e 1361d755

drivers/clk/rockchip/clk-rk3399.c

+3 −3
Original line number Diff line number Diff line
@@ -597,7 +597,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { 
	COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0,

			RK3399_CLKSEL_CON(28), 7, 1, MFLAGS, 0, 7, DFLAGS,

			RK3399_CLKGATE_CON(8), 3, GFLAGS),

	COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", 0,

	COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", CLK_SET_RATE_PARENT,

			RK3399_CLKSEL_CON(96), 0,

			RK3399_CLKGATE_CON(8), 4, GFLAGS,

			&rk3399_i2s0_fracmux),
@@ -607,7 +607,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { 
	COMPOSITE(0, "clk_i2s1_div", mux_pll_src_cpll_gpll_p, 0,

			RK3399_CLKSEL_CON(29), 7, 1, MFLAGS, 0, 7, DFLAGS,

			RK3399_CLKGATE_CON(8), 6, GFLAGS),

	COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", 0,

	COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", CLK_SET_RATE_PARENT,

			RK3399_CLKSEL_CON(97), 0,

			RK3399_CLKGATE_CON(8), 7, GFLAGS,

			&rk3399_i2s1_fracmux),
@@ -617,7 +617,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { 
	COMPOSITE(0, "clk_i2s2_div", mux_pll_src_cpll_gpll_p, 0,

			RK3399_CLKSEL_CON(30), 7, 1, MFLAGS, 0, 7, DFLAGS,

			RK3399_CLKGATE_CON(8), 9, GFLAGS),

	COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", 0,

	COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", CLK_SET_RATE_PARENT,

			RK3399_CLKSEL_CON(98), 0,

			RK3399_CLKGATE_CON(8), 10, GFLAGS,

			&rk3399_i2s2_fracmux),

drivers/clk/rockchip/clk-rk3568.c

+1 −0
Original line number Diff line number Diff line
@@ -78,6 +78,7 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = { 
	RK3036_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0),

	RK3036_PLL_RATE(148500000, 1, 99, 4, 4, 1, 0),

	RK3036_PLL_RATE(135000000, 2, 45, 4, 1, 1, 0),

	RK3036_PLL_RATE(128000000, 1, 16, 3, 1, 1, 0),

	RK3036_PLL_RATE(126400000, 1, 79, 5, 3, 1, 0),

	RK3036_PLL_RATE(119000000, 3, 119, 4, 2, 1, 0),

	RK3036_PLL_RATE(115200000, 1, 24, 5, 1, 1, 0),

drivers/clk/rockchip/clk-rk3588.c

+28 −27
Original line number Diff line number Diff line
@@ -29,7 +29,7 @@ 
 * power, but avoids leaking implementation details into DT or hanging the

 * system.

 */

#define GATE_LINK(_id, cname, pname, linkname, f, o, b, gf) \

#define GATE_LINK(_id, cname, pname, linkedclk, f, o, b, gf) \

	GATE(_id, cname, pname, f, o, b, gf)

#define RK3588_LINKED_CLK		CLK_IS_CRITICAL
@@ -1851,8 +1851,6 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { 
			RK3588_CLKGATE_CON(56), 0, GFLAGS),

	GATE(PCLK_TRNG0, "pclk_trng0", "pclk_vo0_root", 0,

			RK3588_CLKGATE_CON(56), 1, GFLAGS),

	GATE(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", CLK_IGNORE_UNUSED,

			RK3588_CLKGATE_CON(55), 10, GFLAGS),

	COMPOSITE(CLK_I2S4_8CH_TX_SRC, "clk_i2s4_8ch_tx_src", gpll_aupll_p, 0,

			RK3588_CLKSEL_CON(118), 5, 1, MFLAGS, 0, 5, DFLAGS,

			RK3588_CLKGATE_CON(56), 11, GFLAGS),
@@ -1998,8 +1996,6 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { 
			RK3588_CLKGATE_CON(60), 9, GFLAGS),

	GATE(PCLK_TRNG1, "pclk_trng1", "pclk_vo1_root", 0,

			RK3588_CLKGATE_CON(60), 10, GFLAGS),

	GATE(0, "pclk_vo1grf", "pclk_vo1_root", CLK_IGNORE_UNUSED,

			RK3588_CLKGATE_CON(59), 12, GFLAGS),

	GATE(PCLK_S_EDP0, "pclk_s_edp0", "pclk_vo1_s_root", 0,

			RK3588_CLKGATE_CON(59), 14, GFLAGS),

	GATE(PCLK_S_EDP1, "pclk_s_edp1", "pclk_vo1_s_root", 0,
@@ -2433,40 +2429,45 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { 
	GATE(ACLK_AV1, "aclk_av1", "aclk_av1_pre", 0,

			RK3588_CLKGATE_CON(68), 2, GFLAGS),



	GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", "aclk_vi_root", 0, RK3588_CLKGATE_CON(26), 6, GFLAGS),

	GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", "hclk_vi_root", 0, RK3588_CLKGATE_CON(26), 8, GFLAGS),

	GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", "aclk_nvm_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(31), 2, GFLAGS),

	GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 2, GFLAGS),

	GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 3, GFLAGS),

	GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 7, GFLAGS),

	GATE_LINK(ACLK_VDPU_LOW_PRE, "aclk_vdpu_low_pre", "aclk_vdpu_low_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 5, GFLAGS),

	GATE_LINK(ACLK_RKVENC1_PRE, "aclk_rkvenc1_pre", "aclk_rkvenc1_root", "aclk_rkvenc0", 0, RK3588_CLKGATE_CON(48), 3, GFLAGS),

	GATE_LINK(HCLK_RKVENC1_PRE, "hclk_rkvenc1_pre", "hclk_rkvenc1_root", "hclk_rkvenc0", 0, RK3588_CLKGATE_CON(48), 2, GFLAGS),

	GATE_LINK(HCLK_RKVDEC0_PRE, "hclk_rkvdec0_pre", "hclk_rkvdec0_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(40), 5, GFLAGS),

	GATE_LINK(ACLK_RKVDEC0_PRE, "aclk_rkvdec0_pre", "aclk_rkvdec0_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(40), 6, GFLAGS),

	GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 4, GFLAGS),

	GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 5, GFLAGS),

	GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", "aclk_vop_low_root", 0, RK3588_CLKGATE_CON(55), 9, GFLAGS),

	GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", "hclk_vop_root", 0, RK3588_CLKGATE_CON(55), 5, GFLAGS),

	GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 6, GFLAGS),

	GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 9, GFLAGS),

	GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 1, GFLAGS),

	GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 4, GFLAGS),

	GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", "hclk_nvm", 0, RK3588_CLKGATE_CON(75), 1, GFLAGS),

	GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", ACLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 6, GFLAGS),

	GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", HCLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 8, GFLAGS),

	GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", ACLK_NVM_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(31), 2, GFLAGS),

	GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", ACLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(42), 2, GFLAGS),

	GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", HCLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(42), 3, GFLAGS),

	GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(44), 7, GFLAGS),

	GATE_LINK(ACLK_VDPU_LOW_PRE, "aclk_vdpu_low_pre", "aclk_vdpu_low_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(44), 5, GFLAGS),

	GATE_LINK(ACLK_RKVENC1_PRE, "aclk_rkvenc1_pre", "aclk_rkvenc1_root", ACLK_RKVENC0, 0, RK3588_CLKGATE_CON(48), 3, GFLAGS),

	GATE_LINK(HCLK_RKVENC1_PRE, "hclk_rkvenc1_pre", "hclk_rkvenc1_root", HCLK_RKVENC0, 0, RK3588_CLKGATE_CON(48), 2, GFLAGS),

	GATE_LINK(HCLK_RKVDEC0_PRE, "hclk_rkvdec0_pre", "hclk_rkvdec0_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(40), 5, GFLAGS),

	GATE_LINK(ACLK_RKVDEC0_PRE, "aclk_rkvdec0_pre", "aclk_rkvdec0_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(40), 6, GFLAGS),

	GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(41), 4, GFLAGS),

	GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(41), 5, GFLAGS),

	GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", ACLK_VOP_LOW_ROOT, 0, RK3588_CLKGATE_CON(55), 9, GFLAGS),

	GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", HCLK_VOP_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(55), 5, GFLAGS),

	GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", ACLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(59), 6, GFLAGS),

	GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", HCLK_VO1USB_TOP_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(59), 9, GFLAGS),

	GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(68), 1, GFLAGS),

	GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(68), 4, GFLAGS),

	GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", HCLK_NVM, 0, RK3588_CLKGATE_CON(75), 1, GFLAGS),

	GATE_LINK(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", HCLK_VO0, CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(55), 10, GFLAGS),

	GATE_LINK(PCLK_VO1GRF, "pclk_vo1grf", "pclk_vo1_root", HCLK_VO1, CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(59), 12, GFLAGS),

};



static void __init rk3588_clk_init(struct device_node *np)

{

	struct rockchip_clk_provider *ctx;

	unsigned long clk_nr_clks;

	void __iomem *reg_base;



	clk_nr_clks = rockchip_clk_find_max_clk_id(rk3588_clk_branches,

					ARRAY_SIZE(rk3588_clk_branches)) + 1;

	reg_base = of_iomap(np, 0);

	if (!reg_base) {

		pr_err("%s: could not map cru region\n", __func__);

		return;

	}



	ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);

	ctx = rockchip_clk_init(np, reg_base, clk_nr_clks);

	if (IS_ERR(ctx)) {

		pr_err("%s: rockchip clk init failed\n", __func__);

		iounmap(reg_base);

drivers/clk/rockchip/clk.c

+17 −0
Original line number Diff line number Diff line
@@ -429,6 +429,23 @@ void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx, 
}

EXPORT_SYMBOL_GPL(rockchip_clk_register_plls);



unsigned long rockchip_clk_find_max_clk_id(struct rockchip_clk_branch *list,

					   unsigned int nr_clk)

{

	unsigned long max = 0;

	unsigned int idx;



	for (idx = 0; idx < nr_clk; idx++, list++) {

		if (list->id > max)

			max = list->id;

		if (list->child && list->child->id > max)

			max = list->id;

	}



	return max;

}

EXPORT_SYMBOL_GPL(rockchip_clk_find_max_clk_id);



void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,

				    struct rockchip_clk_branch *list,

				    unsigned int nr_clk)

drivers/clk/rockchip/clk.h

+2 −0
Original line number Diff line number Diff line
@@ -973,6 +973,8 @@ struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np, 
			void __iomem *base, unsigned long nr_clks);

void rockchip_clk_of_add_provider(struct device_node *np,

				struct rockchip_clk_provider *ctx);

unsigned long rockchip_clk_find_max_clk_id(struct rockchip_clk_branch *list,

					   unsigned int nr_clk);

void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,

				    struct rockchip_clk_branch *list,

				    unsigned int nr_clk);