Commit 3e8008fc authored by Claudiu Beznea's avatar Claudiu Beznea Committed by Geert Uytterhoeven
Browse files

clk: renesas: rzg2l: Remove CPG_SDHI_DSEL from generic header 



Remove CPG_SDHI_DSEL and its bits from the generic header as RZ/G3S has
different offset registers and bits for this, thus avoid mixing them.

Signed-off-by: default avatarClaudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230929053915.1530607-10-claudiu.beznea@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 97c1c4cc

drivers/clk/renesas/r9a07g043-cpg.c

+7 −0
Original line number Diff line number Diff line
@@ -14,6 +14,13 @@ 


#include "rzg2l-cpg.h"



/* Specific registers. */

#define CPG_PL2SDHI_DSEL	(0x218)



/* Clock select configuration. */

#define SEL_SDHI0		SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 0, 2)

#define SEL_SDHI1		SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 4, 2)



enum clk_ids {

	/* Core Clock Outputs exported to DT */

	LAST_DT_CORE_CLK = R9A07G043_CLK_P0_DIV2,

drivers/clk/renesas/r9a07g044-cpg.c

+7 −0
Original line number Diff line number Diff line
@@ -15,6 +15,13 @@ 


#include "rzg2l-cpg.h"



/* Specific registers. */

#define CPG_PL2SDHI_DSEL	(0x218)



/* Clock select configuration. */

#define SEL_SDHI0		SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 0, 2)

#define SEL_SDHI1		SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 4, 2)



enum clk_ids {

	/* Core Clock Outputs exported to DT */

	LAST_DT_CORE_CLK = R9A07G054_CLK_DRP_A,

drivers/clk/renesas/rzg2l-cpg.h

+0 −4
Original line number Diff line number Diff line
@@ -19,7 +19,6 @@ 
#define CPG_PL2_DDIV		(0x204)

#define CPG_PL3A_DDIV		(0x208)

#define CPG_PL6_DDIV		(0x210)

#define CPG_PL2SDHI_DSEL	(0x218)

#define CPG_CLKSTATUS		(0x280)

#define CPG_PL3_SSEL		(0x408)

#define CPG_PL6_SSEL		(0x414)
@@ -69,9 +68,6 @@ 
#define SEL_PLL6_2	SEL_PLL_PACK(CPG_PL6_ETH_SSEL, 0, 1)

#define SEL_GPU2	SEL_PLL_PACK(CPG_PL6_SSEL, 12, 1)



#define SEL_SDHI0	DDIV_PACK(CPG_PL2SDHI_DSEL, 0, 2)

#define SEL_SDHI1	DDIV_PACK(CPG_PL2SDHI_DSEL, 4, 2)



#define EXTAL_FREQ_IN_MEGA_HZ	(24)



/**