Commit 3ea94399 authored by Dillon Varone's avatar Dillon Varone Committed by Alex Deucher
Browse files

drm/amd/display: Add SMU interface to get UMC count for dcn401 



[WHY&HOW]
BIOS table will not always contain accurate UMC channel info when
harvesting is enabled, so get the correct info from SMU.

Reviewed-by: default avatarAlvin Lee <alvin.lee2@amd.com>
Signed-off-by: default avatarDillon Varone <dillon.varone@amd.com>
Signed-off-by: default avatarTom Chung <chiahsuan.chung@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e2c4c6c1

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dalsmc.h

+3 −1
Original line number Diff line number Diff line
@@ -43,7 +43,9 @@ 
#define DALSMC_MSG_ActiveUclkFclk                 0x18

#define DALSMC_MSG_IdleUclkFclk                   0x19

#define DALSMC_MSG_SetUclkPstateAllow             0x1A

#define DALSMC_Message_Count                      0x1B

#define DALSMC_MSG_SubvpUclkFclk                  0x1B

#define DALSMC_MSG_GetNumUmcChannels              0x1C

#define DALSMC_Message_Count                      0x1D



typedef enum {

  FCLK_SWITCH_DISALLOW,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

+9 −0
Original line number Diff line number Diff line
@@ -1403,6 +1403,15 @@ static void dcn401_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base) 
	if (clk_mgr->dpm_present && !num_levels)

		clk_mgr->dpm_present = false;



	clk_mgr_base->bw_params->num_channels = dcn401_smu_get_num_of_umc_channels(clk_mgr);

	if (clk_mgr_base->ctx->dc_bios) {

		/* use BIOS values if none provided by PMFW */

		if (clk_mgr_base->bw_params->num_channels == 0) {

			clk_mgr_base->bw_params->num_channels = clk_mgr_base->ctx->dc_bios->vram_info.num_chans;

		}

		clk_mgr_base->bw_params->dram_channel_width_bytes = clk_mgr_base->ctx->dc_bios->vram_info.dram_channel_width_bytes;

	}



	/* Refresh bounding box */

	clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box(

			clk_mgr->base.ctx->dc, clk_mgr_base->bw_params);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

+14 −0
Original line number Diff line number Diff line
@@ -25,6 +25,9 @@ 
#ifndef DALSMC_MSG_SubvpUclkFclk

#define DALSMC_MSG_SubvpUclkFclk 0x1B

#endif

#ifndef DALSMC_MSG_GetNumUmcChannels

#define DALSMC_MSG_GetNumUmcChannels 0x1C

#endif



/*

 * Function to be used instead of REG_WAIT macro because the wait ends when
@@ -334,3 +337,14 @@ void dcn401_smu_set_num_of_displays(struct clk_mgr_internal *clk_mgr, uint32_t n 
	dcn401_smu_send_msg_with_param(clk_mgr,

			DALSMC_MSG_NumOfDisplays, num_displays, NULL);

}



unsigned int dcn401_smu_get_num_of_umc_channels(struct clk_mgr_internal *clk_mgr)

{

	unsigned int response = 0;



	dcn401_smu_send_msg_with_param(clk_mgr, DALSMC_MSG_GetNumUmcChannels, 0, &response);



	smu_print("SMU Get Num UMC Channels: num_umc_channels = %d\n", response);



	return response;

}

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

+1 −0
Original line number Diff line number Diff line
@@ -28,5 +28,6 @@ bool dcn401_smu_set_subvp_uclk_fclk_hardmin(struct clk_mgr_internal *clk_mgr, 
		uint16_t fclk_freq_mhz);

void dcn401_smu_set_min_deep_sleep_dcef_clk(struct clk_mgr_internal *clk_mgr, uint32_t freq_mhz);

void dcn401_smu_set_num_of_displays(struct clk_mgr_internal *clk_mgr, uint32_t num_displays);

unsigned int dcn401_smu_get_num_of_umc_channels(struct clk_mgr_internal *clk_mgr);



#endif /* __DCN401_CLK_MGR_SMU_MSG_H_ */

drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

+7 −2
Original line number Diff line number Diff line
@@ -294,12 +294,17 @@ void dml21_apply_soc_bb_overrides(struct dml2_initialize_instance_in_out *dml_in 
		dml_soc_bb->power_management_parameters.stutter_exit_latency_us =

			(in_dc->ctx->dc_bios->bb_info.dram_sr_exit_latency_100ns + 9) / 10;



	if (in_dc->ctx->dc_bios->vram_info.num_chans) {

	if (dc_bw_params->num_channels) {

		dml_clk_table->dram_config.channel_count = dc_bw_params->num_channels;

		dml_soc_bb->mall_allocated_for_dcn_mbytes = in_dc->caps.mall_size_total / 1048576;

	} else if (in_dc->ctx->dc_bios->vram_info.num_chans) {

		dml_clk_table->dram_config.channel_count = in_dc->ctx->dc_bios->vram_info.num_chans;

		dml_soc_bb->mall_allocated_for_dcn_mbytes = in_dc->caps.mall_size_total / 1048576;

	}



	if (in_dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) {

	if (dc_bw_params->dram_channel_width_bytes) {

		dml_clk_table->dram_config.channel_width_bytes = dc_bw_params->dram_channel_width_bytes;

	} else if (in_dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) {

		dml_clk_table->dram_config.channel_width_bytes = in_dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;

	}