Commit 3eb1b39b authored by Alexander Stein's avatar Alexander Stein Committed by Shawn Guo
Browse files

arm64: dts: freescale: Add dual-channel LVDS overlay for TQMa8MPxL 



This adds an overlay for the supported LVDS display AUO G133HAN01.
Configure the video PLL frequency to exactly match typical pixel clock of
141.200 MHz.

Signed-off-by: default avatarAlexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 85e51f62

arch/arm64/boot/dts/freescale/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -129,7 +129,9 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-dev.dtb 
dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-yavia.dtb



imx8mp-tqma8mpql-mba8mpxl-lvds-dtbs += imx8mp-tqma8mpql-mba8mpxl.dtb imx8mp-tqma8mpql-mba8mpxl-lvds.dtbo

imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01-dtbs += imx8mp-tqma8mpql-mba8mpxl.dtb imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtbo

dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl-lvds.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtb



dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mq-hummingboard-pulse.dtb

arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtso

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// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)

/*

 * Copyright (c) 2023 TQ-Systems GmbH <linux@ew.tq-group.com>,

 * D-82229 Seefeld, Germany.

 * Author: Alexander Stein

 */



/dts-v1/;

/plugin/;



#include <dt-bindings/clock/imx8mp-clock.h>



&{/} {

	compatible = "tq,imx8mp-tqma8mpql-mba8mpxl", "tq,imx8mp-tqma8mpql", "fsl,imx8mp";

};



&backlight_lvds {

	status = "okay";

};



&display {

	compatible = "auo,g133han01";

	status = "okay";



	ports {

		#address-cells = <1>;

		#size-cells = <0>;



		port@0 {

			reg = <0>;

			dual-lvds-odd-pixels;



			panel_in_lvds0: endpoint {

				remote-endpoint = <&ldb_lvds_ch0>;

			};

		};



		port@1 {

			reg = <1>;

			dual-lvds-even-pixels;



			panel_in_lvds1: endpoint {

				remote-endpoint = <&ldb_lvds_ch1>;

			};

		};

	};

};



&lcdif2 {

	status = "okay";

};



&lvds_bridge {

	assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>,

				 <&clk IMX8MP_VIDEO_PLL1>;

	assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;

	assigned-clock-rates = <0>, <988400000>;

	status = "okay";



	ports {

		port@1 {

			ldb_lvds_ch0: endpoint {

				remote-endpoint = <&panel_in_lvds0>;

			};

		};



		port@2 {

			ldb_lvds_ch1: endpoint {

				remote-endpoint = <&panel_in_lvds1>;

			};

		};

	};

};



&pwm2 {

	status = "okay";

};