Commit 3ec1a42f authored by Lijo Lazar's avatar Lijo Lazar Committed by Alex Deucher
Browse files

drm/amd/pm: Use generic dpm table for SMUv11 SOCs 



Remove SMUv11 specific DPM table and use the generic dpm table
structure.

Signed-off-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8c5c0ea2

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h

+14 −27
Original line number Diff line number Diff line
@@ -53,7 +53,6 @@ 


#define SMU11_TOOL_SIZE			0x19000



#define MAX_DPM_LEVELS 16

#define MAX_PCIE_CONF 2



#define CTF_OFFSET_EDGE			5
@@ -80,18 +79,6 @@ struct smu_11_0_max_sustainable_clocks { 
	uint32_t soc_clock;

};



struct smu_11_0_dpm_clk_level {

	bool				enabled;

	uint32_t			value;

};



struct smu_11_0_dpm_table {

	uint32_t			min;        /* MHz */

	uint32_t			max;        /* MHz */

	uint32_t			count;

	bool				is_fine_grained;

	struct smu_11_0_dpm_clk_level	dpm_levels[MAX_DPM_LEVELS];

};



struct smu_11_0_pcie_table {

	uint8_t  pcie_gen[MAX_PCIE_CONF];
@@ -99,19 +86,19 @@ struct smu_11_0_pcie_table { 
};



struct smu_11_0_dpm_tables {

	struct smu_11_0_dpm_table        soc_table;

	struct smu_11_0_dpm_table        gfx_table;

	struct smu_11_0_dpm_table        uclk_table;

	struct smu_11_0_dpm_table        eclk_table;

	struct smu_11_0_dpm_table        vclk_table;

	struct smu_11_0_dpm_table        vclk1_table;

	struct smu_11_0_dpm_table        dclk_table;

	struct smu_11_0_dpm_table        dclk1_table;

	struct smu_11_0_dpm_table        dcef_table;

	struct smu_11_0_dpm_table        pixel_table;

	struct smu_11_0_dpm_table        display_table;

	struct smu_11_0_dpm_table        phy_table;

	struct smu_11_0_dpm_table        fclk_table;

	struct smu_dpm_table             soc_table;

	struct smu_dpm_table             gfx_table;

	struct smu_dpm_table             uclk_table;

	struct smu_dpm_table             eclk_table;

	struct smu_dpm_table             vclk_table;

	struct smu_dpm_table             vclk1_table;

	struct smu_dpm_table             dclk_table;

	struct smu_dpm_table             dclk1_table;

	struct smu_dpm_table             dcef_table;

	struct smu_dpm_table             pixel_table;

	struct smu_dpm_table             display_table;

	struct smu_dpm_table             phy_table;

	struct smu_dpm_table             fclk_table;

	struct smu_11_0_pcie_table       pcie_table;

};
@@ -279,7 +266,7 @@ int smu_v11_0_get_dpm_level_count(struct smu_context *smu, 


int smu_v11_0_set_single_dpm_table(struct smu_context *smu,

				   enum smu_clk_type clk_type,

				   struct smu_11_0_dpm_table *single_dpm_table);

				   struct smu_dpm_table *single_dpm_table);



int smu_v11_0_get_current_pcie_link_width_level(struct smu_context *smu);

drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

+25 −32
Original line number Diff line number Diff line
@@ -362,79 +362,75 @@ static int arcturus_set_default_dpm_table(struct smu_context *smu) 
{

	struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;

	PPTable_t *driver_ppt = smu->smu_table.driver_pptable;

	struct smu_11_0_dpm_table *dpm_table = NULL;

	struct smu_dpm_table *dpm_table = NULL;

	int ret = 0;



	/* socclk dpm table setup */

	dpm_table = &dpm_context->dpm_tables.soc_table;

	dpm_table->clk_type = SMU_SOCCLK;

	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {

		ret = smu_v11_0_set_single_dpm_table(smu,

						     SMU_SOCCLK,

						     dpm_table);

		if (ret)

			return ret;

		dpm_table->is_fine_grained =

			!driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;

		if (!driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete)

			dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED;

	} else {

		dpm_table->count = 1;

		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;

		dpm_table->dpm_levels[0].enabled = true;

		dpm_table->min = dpm_table->dpm_levels[0].value;

		dpm_table->max = dpm_table->dpm_levels[0].value;

	}



	/* gfxclk dpm table setup */

	dpm_table = &dpm_context->dpm_tables.gfx_table;

	dpm_table->clk_type = SMU_GFXCLK;

	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {

		ret = smu_v11_0_set_single_dpm_table(smu,

						     SMU_GFXCLK,

						     dpm_table);

		if (ret)

			return ret;

		dpm_table->is_fine_grained =

			!driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;

		if (!driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete)

			dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED;

	} else {

		dpm_table->count = 1;

		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;

		dpm_table->dpm_levels[0].enabled = true;

		dpm_table->min = dpm_table->dpm_levels[0].value;

		dpm_table->max = dpm_table->dpm_levels[0].value;

	}



	/* memclk dpm table setup */

	dpm_table = &dpm_context->dpm_tables.uclk_table;

	dpm_table->clk_type = SMU_UCLK;

	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {

		ret = smu_v11_0_set_single_dpm_table(smu,

						     SMU_UCLK,

						     dpm_table);

		if (ret)

			return ret;

		dpm_table->is_fine_grained =

			!driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;

		if (!driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete)

			dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED;

	} else {

		dpm_table->count = 1;

		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;

		dpm_table->dpm_levels[0].enabled = true;

		dpm_table->min = dpm_table->dpm_levels[0].value;

		dpm_table->max = dpm_table->dpm_levels[0].value;

	}



	/* fclk dpm table setup */

	dpm_table = &dpm_context->dpm_tables.fclk_table;

	dpm_table->clk_type = SMU_FCLK;

	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {

		ret = smu_v11_0_set_single_dpm_table(smu,

						     SMU_FCLK,

						     dpm_table);

		if (ret)

			return ret;

		dpm_table->is_fine_grained =

			!driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete;

		if (!driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete)

			dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED;

	} else {

		dpm_table->count = 1;

		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;

		dpm_table->dpm_levels[0].enabled = true;

		dpm_table->min = dpm_table->dpm_levels[0].value;

		dpm_table->max = dpm_table->dpm_levels[0].value;

	}



	/* XGMI PLPD is supported by 54.23.0 and onwards */
@@ -572,23 +568,20 @@ static int arcturus_populate_umd_state_clk(struct smu_context *smu) 
{

	struct smu_11_0_dpm_context *dpm_context =

				smu->smu_dpm.dpm_context;

	struct smu_11_0_dpm_table *gfx_table =

				&dpm_context->dpm_tables.gfx_table;

	struct smu_11_0_dpm_table *mem_table =

				&dpm_context->dpm_tables.uclk_table;

	struct smu_11_0_dpm_table *soc_table =

				&dpm_context->dpm_tables.soc_table;

	struct smu_dpm_table *gfx_table = &dpm_context->dpm_tables.gfx_table;

	struct smu_dpm_table *mem_table = &dpm_context->dpm_tables.uclk_table;

	struct smu_dpm_table *soc_table = &dpm_context->dpm_tables.soc_table;

	struct smu_umd_pstate_table *pstate_table =

				&smu->pstate_table;



	pstate_table->gfxclk_pstate.min = gfx_table->min;

	pstate_table->gfxclk_pstate.peak = gfx_table->max;

	pstate_table->gfxclk_pstate.min = SMU_DPM_TABLE_MIN(gfx_table);

	pstate_table->gfxclk_pstate.peak = SMU_DPM_TABLE_MAX(gfx_table);



	pstate_table->uclk_pstate.min = mem_table->min;

	pstate_table->uclk_pstate.peak = mem_table->max;

	pstate_table->uclk_pstate.min = SMU_DPM_TABLE_MIN(mem_table);

	pstate_table->uclk_pstate.peak = SMU_DPM_TABLE_MAX(mem_table);



	pstate_table->socclk_pstate.min = soc_table->min;

	pstate_table->socclk_pstate.peak = soc_table->max;

	pstate_table->socclk_pstate.min = SMU_DPM_TABLE_MIN(soc_table);

	pstate_table->socclk_pstate.peak = SMU_DPM_TABLE_MAX(soc_table);



	if (gfx_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&

	    mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL &&
@@ -613,7 +606,7 @@ static int arcturus_populate_umd_state_clk(struct smu_context *smu) 


static void arcturus_get_clk_table(struct smu_context *smu,

				   struct pp_clock_levels_with_latency *clocks,

				   struct smu_11_0_dpm_table *dpm_table)

				   struct smu_dpm_table *dpm_table)

{

	uint32_t i;
@@ -802,7 +795,7 @@ static int arcturus_emit_clk_levels(struct smu_context *smu, 
{

	int ret = 0;

	struct pp_clock_levels_with_latency clocks;

	struct smu_11_0_dpm_table *single_dpm_table;

	struct smu_dpm_table *single_dpm_table;

	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;

	struct smu_11_0_dpm_context *dpm_context = NULL;

	uint32_t gen_speed, lane_width;
@@ -1003,7 +996,7 @@ static int arcturus_force_clk_levels(struct smu_context *smu, 
			enum smu_clk_type type, uint32_t mask)

{

	struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;

	struct smu_11_0_dpm_table *single_dpm_table = NULL;

	struct smu_dpm_table *single_dpm_table = NULL;

	uint32_t soft_min_level, soft_max_level;

	int ret = 0;

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

+39 −51
Original line number Diff line number Diff line
@@ -967,169 +967,160 @@ static int navi10_set_default_dpm_table(struct smu_context *smu) 
{

	struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;

	PPTable_t *driver_ppt = smu->smu_table.driver_pptable;

	struct smu_11_0_dpm_table *dpm_table;

	struct smu_dpm_table *dpm_table;

	int ret = 0;



	/* socclk dpm table setup */

	dpm_table = &dpm_context->dpm_tables.soc_table;

	dpm_table->clk_type = SMU_SOCCLK;

	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {

		ret = smu_v11_0_set_single_dpm_table(smu,

						     SMU_SOCCLK,

						     dpm_table);

		if (ret)

			return ret;

		dpm_table->is_fine_grained =

			!driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;

		if (!driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete)

			dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED;

	} else {

		dpm_table->count = 1;

		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;

		dpm_table->dpm_levels[0].enabled = true;

		dpm_table->min = dpm_table->dpm_levels[0].value;

		dpm_table->max = dpm_table->dpm_levels[0].value;

	}



	/* gfxclk dpm table setup */

	dpm_table = &dpm_context->dpm_tables.gfx_table;

	dpm_table->clk_type = SMU_GFXCLK;

	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {

		ret = smu_v11_0_set_single_dpm_table(smu,

						     SMU_GFXCLK,

						     dpm_table);

		if (ret)

			return ret;

		dpm_table->is_fine_grained =

			!driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;

		if (!driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete)

			dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED;

	} else {

		dpm_table->count = 1;

		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;

		dpm_table->dpm_levels[0].enabled = true;

		dpm_table->min = dpm_table->dpm_levels[0].value;

		dpm_table->max = dpm_table->dpm_levels[0].value;

	}



	/* uclk dpm table setup */

	dpm_table = &dpm_context->dpm_tables.uclk_table;

	dpm_table->clk_type = SMU_UCLK;

	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {

		ret = smu_v11_0_set_single_dpm_table(smu,

						     SMU_UCLK,

						     dpm_table);

		if (ret)

			return ret;

		dpm_table->is_fine_grained =

			!driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;

		if (!driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete)

			dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED;

	} else {

		dpm_table->count = 1;

		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;

		dpm_table->dpm_levels[0].enabled = true;

		dpm_table->min = dpm_table->dpm_levels[0].value;

		dpm_table->max = dpm_table->dpm_levels[0].value;

	}



	/* vclk dpm table setup */

	dpm_table = &dpm_context->dpm_tables.vclk_table;

	dpm_table->clk_type = SMU_VCLK;

	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {

		ret = smu_v11_0_set_single_dpm_table(smu,

						     SMU_VCLK,

						     dpm_table);

		if (ret)

			return ret;

		dpm_table->is_fine_grained =

			!driver_ppt->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete;

		if (!driver_ppt->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete)

			dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED;

	} else {

		dpm_table->count = 1;

		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;

		dpm_table->dpm_levels[0].enabled = true;

		dpm_table->min = dpm_table->dpm_levels[0].value;

		dpm_table->max = dpm_table->dpm_levels[0].value;

	}



	/* dclk dpm table setup */

	dpm_table = &dpm_context->dpm_tables.dclk_table;

	dpm_table->clk_type = SMU_DCLK;

	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {

		ret = smu_v11_0_set_single_dpm_table(smu,

						     SMU_DCLK,

						     dpm_table);

		if (ret)

			return ret;

		dpm_table->is_fine_grained =

			!driver_ppt->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete;

		if (!driver_ppt->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete)

			dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED;

	} else {

		dpm_table->count = 1;

		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;

		dpm_table->dpm_levels[0].enabled = true;

		dpm_table->min = dpm_table->dpm_levels[0].value;

		dpm_table->max = dpm_table->dpm_levels[0].value;

	}



	/* dcefclk dpm table setup */

	dpm_table = &dpm_context->dpm_tables.dcef_table;

	dpm_table->clk_type = SMU_DCEFCLK;

	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {

		ret = smu_v11_0_set_single_dpm_table(smu,

						     SMU_DCEFCLK,

						     dpm_table);

		if (ret)

			return ret;

		dpm_table->is_fine_grained =

			!driver_ppt->DpmDescriptor[PPCLK_DCEFCLK].SnapToDiscrete;

		if (!driver_ppt->DpmDescriptor[PPCLK_DCEFCLK].SnapToDiscrete)

			dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED;

	} else {

		dpm_table->count = 1;

		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;

		dpm_table->dpm_levels[0].enabled = true;

		dpm_table->min = dpm_table->dpm_levels[0].value;

		dpm_table->max = dpm_table->dpm_levels[0].value;

	}



	/* pixelclk dpm table setup */

	dpm_table = &dpm_context->dpm_tables.pixel_table;

	dpm_table->clk_type = SMU_PIXCLK;

	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {

		ret = smu_v11_0_set_single_dpm_table(smu,

						     SMU_PIXCLK,

						     dpm_table);

		if (ret)

			return ret;

		dpm_table->is_fine_grained =

			!driver_ppt->DpmDescriptor[PPCLK_PIXCLK].SnapToDiscrete;

		if (!driver_ppt->DpmDescriptor[PPCLK_PIXCLK].SnapToDiscrete)

			dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED;

	} else {

		dpm_table->count = 1;

		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;

		dpm_table->dpm_levels[0].enabled = true;

		dpm_table->min = dpm_table->dpm_levels[0].value;

		dpm_table->max = dpm_table->dpm_levels[0].value;

	}



	/* displayclk dpm table setup */

	dpm_table = &dpm_context->dpm_tables.display_table;

	dpm_table->clk_type = SMU_DISPCLK;

	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {

		ret = smu_v11_0_set_single_dpm_table(smu,

						     SMU_DISPCLK,

						     dpm_table);

		if (ret)

			return ret;

		dpm_table->is_fine_grained =

			!driver_ppt->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete;

		if (!driver_ppt->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete)

			dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED;

	} else {

		dpm_table->count = 1;

		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;

		dpm_table->dpm_levels[0].enabled = true;

		dpm_table->min = dpm_table->dpm_levels[0].value;

		dpm_table->max = dpm_table->dpm_levels[0].value;

	}



	/* phyclk dpm table setup */

	dpm_table = &dpm_context->dpm_tables.phy_table;

	dpm_table->clk_type = SMU_PHYCLK;

	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {

		ret = smu_v11_0_set_single_dpm_table(smu,

						     SMU_PHYCLK,

						     dpm_table);

		if (ret)

			return ret;

		dpm_table->is_fine_grained =

			!driver_ppt->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete;

		if (!driver_ppt->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete)

			dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED;

	} else {

		dpm_table->count = 1;

		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;

		dpm_table->dpm_levels[0].enabled = true;

		dpm_table->min = dpm_table->dpm_levels[0].value;

		dpm_table->max = dpm_table->dpm_levels[0].value;

	}



	return 0;
@@ -1519,18 +1510,15 @@ static int navi10_populate_umd_state_clk(struct smu_context *smu) 
{

	struct smu_11_0_dpm_context *dpm_context =

				smu->smu_dpm.dpm_context;

	struct smu_11_0_dpm_table *gfx_table =

				&dpm_context->dpm_tables.gfx_table;

	struct smu_11_0_dpm_table *mem_table =

				&dpm_context->dpm_tables.uclk_table;

	struct smu_11_0_dpm_table *soc_table =

				&dpm_context->dpm_tables.soc_table;

	struct smu_dpm_table *gfx_table = &dpm_context->dpm_tables.gfx_table;

	struct smu_dpm_table *mem_table = &dpm_context->dpm_tables.uclk_table;

	struct smu_dpm_table *soc_table = &dpm_context->dpm_tables.soc_table;

	struct smu_umd_pstate_table *pstate_table =

				&smu->pstate_table;

	struct amdgpu_device *adev = smu->adev;

	uint32_t sclk_freq;



	pstate_table->gfxclk_pstate.min = gfx_table->min;

	pstate_table->gfxclk_pstate.min = SMU_DPM_TABLE_MIN(gfx_table);

	switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {

	case IP_VERSION(11, 0, 0):

		switch (adev->pdev->revision) {
@@ -1579,15 +1567,15 @@ static int navi10_populate_umd_state_clk(struct smu_context *smu) 
	}

	pstate_table->gfxclk_pstate.peak = sclk_freq;



	pstate_table->uclk_pstate.min = mem_table->min;

	pstate_table->uclk_pstate.peak = mem_table->max;

	pstate_table->uclk_pstate.min = SMU_DPM_TABLE_MIN(mem_table);

	pstate_table->uclk_pstate.peak = SMU_DPM_TABLE_MAX(mem_table);



	pstate_table->socclk_pstate.min = soc_table->min;

	pstate_table->socclk_pstate.peak = soc_table->max;

	pstate_table->socclk_pstate.min = SMU_DPM_TABLE_MIN(soc_table);

	pstate_table->socclk_pstate.peak = SMU_DPM_TABLE_MAX(soc_table);



	if (gfx_table->max > NAVI10_UMD_PSTATE_PROFILING_GFXCLK &&

	    mem_table->max > NAVI10_UMD_PSTATE_PROFILING_MEMCLK &&

	    soc_table->max > NAVI10_UMD_PSTATE_PROFILING_SOCCLK) {

	if (SMU_DPM_TABLE_MAX(gfx_table) > NAVI10_UMD_PSTATE_PROFILING_GFXCLK &&

	    SMU_DPM_TABLE_MAX(mem_table) > NAVI10_UMD_PSTATE_PROFILING_MEMCLK &&

	    SMU_DPM_TABLE_MAX(soc_table) > NAVI10_UMD_PSTATE_PROFILING_SOCCLK) {

		pstate_table->gfxclk_pstate.standard =

			NAVI10_UMD_PSTATE_PROFILING_GFXCLK;

		pstate_table->uclk_pstate.standard =

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

+42 −53

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

+16 −24
Original line number Diff line number Diff line
@@ -1859,12 +1859,9 @@ int smu_v11_0_set_performance_level(struct smu_context *smu, 
{

	struct smu_11_0_dpm_context *dpm_context =

				smu->smu_dpm.dpm_context;

	struct smu_11_0_dpm_table *gfx_table =

				&dpm_context->dpm_tables.gfx_table;

	struct smu_11_0_dpm_table *mem_table =

				&dpm_context->dpm_tables.uclk_table;

	struct smu_11_0_dpm_table *soc_table =

				&dpm_context->dpm_tables.soc_table;

	struct smu_dpm_table *gfx_table = &dpm_context->dpm_tables.gfx_table;

	struct smu_dpm_table *mem_table = &dpm_context->dpm_tables.uclk_table;

	struct smu_dpm_table *soc_table = &dpm_context->dpm_tables.soc_table;

	struct smu_umd_pstate_table *pstate_table =

				&smu->pstate_table;

	struct amdgpu_device *adev = smu->adev;
@@ -1876,22 +1873,22 @@ int smu_v11_0_set_performance_level(struct smu_context *smu, 


	switch (level) {

	case AMD_DPM_FORCED_LEVEL_HIGH:

		sclk_min = sclk_max = gfx_table->max;

		mclk_min = mclk_max = mem_table->max;

		socclk_min = socclk_max = soc_table->max;

		sclk_min = sclk_max = SMU_DPM_TABLE_MAX(gfx_table);

		mclk_min = mclk_max = SMU_DPM_TABLE_MAX(mem_table);

		socclk_min = socclk_max = SMU_DPM_TABLE_MAX(soc_table);

		break;

	case AMD_DPM_FORCED_LEVEL_LOW:

		sclk_min = sclk_max = gfx_table->min;

		mclk_min = mclk_max = mem_table->min;

		socclk_min = socclk_max = soc_table->min;

		sclk_min = sclk_max = SMU_DPM_TABLE_MIN(gfx_table);

		mclk_min = mclk_max = SMU_DPM_TABLE_MIN(mem_table);

		socclk_min = socclk_max = SMU_DPM_TABLE_MIN(soc_table);

		break;

	case AMD_DPM_FORCED_LEVEL_AUTO:

		sclk_min = gfx_table->min;

		sclk_max = gfx_table->max;

		mclk_min = mem_table->min;

		mclk_max = mem_table->max;

		socclk_min = soc_table->min;

		socclk_max = soc_table->max;

		sclk_min = SMU_DPM_TABLE_MIN(gfx_table);

		sclk_max = SMU_DPM_TABLE_MAX(gfx_table);

		mclk_min = SMU_DPM_TABLE_MIN(mem_table);

		mclk_max = SMU_DPM_TABLE_MAX(mem_table);

		socclk_min = SMU_DPM_TABLE_MIN(soc_table);

		socclk_max = SMU_DPM_TABLE_MAX(soc_table);

		auto_level = true;

		break;

	case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
@@ -2028,7 +2025,7 @@ int smu_v11_0_get_dpm_level_count(struct smu_context *smu, 


int smu_v11_0_set_single_dpm_table(struct smu_context *smu,

				   enum smu_clk_type clk_type,

				   struct smu_11_0_dpm_table *single_dpm_table)

				   struct smu_dpm_table *single_dpm_table)

{

	int ret = 0;

	uint32_t clk;
@@ -2054,11 +2051,6 @@ int smu_v11_0_set_single_dpm_table(struct smu_context *smu, 


		single_dpm_table->dpm_levels[i].value = clk;

		single_dpm_table->dpm_levels[i].enabled = true;



		if (i == 0)

			single_dpm_table->min = clk;

		else if (i == single_dpm_table->count - 1)

			single_dpm_table->max = clk;

	}



	return 0;