Commit 3ee92565 authored Mar 28, 2023 by Anup Patel Committed by Marc Zyngier Apr 08, 2023

RISC-V: Clear SIP bit only when using SBI IPI operations



The software interrupt pending (i.e. [M|S]SIP) bit is writeable for
S-mode but read-only for M-mode so we clear this bit only when using
SBI IPI operations.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20230328035223.1480939-2-apatel@ventanamicro.com

parent 197b6b60

arch/riscv/kernel/sbi.c

+7 −1

Original line number	Diff line number	Diff line
		@@ -646,8 +646,14 @@ static void sbi_send_cpumask_ipi(const struct cpumask *target)
		sbi_send_ipi(target);
		}

		static void sbi_ipi_clear(void)
		{
		csr_clear(CSR_IP, IE_SIE);
		}

		static const struct riscv_ipi_ops sbi_ipi_ops = {
		.ipi_inject = sbi_send_cpumask_ipi
		.ipi_inject = sbi_send_cpumask_ipi,
		.ipi_clear = sbi_ipi_clear
		};

		void __init sbi_init(void)

arch/riscv/kernel/smp.c

+0 −2

Original line number	Diff line number	Diff line
		@@ -112,8 +112,6 @@ void riscv_clear_ipi(void)
		{
		if (ipi_ops && ipi_ops->ipi_clear)
		ipi_ops->ipi_clear();

		csr_clear(CSR_IP, IE_SIE);
		}
		EXPORT_SYMBOL_GPL(riscv_clear_ipi);