Commit 3f0b3629 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/controller/cadence' 

- Drop a runtime PM 'put' to resolve a runtime atomic count underflow (Hans
  Zhang)

- Use shared PCIE_MSG_CODE_* definitions and remove duplicate
  cdns_pcie_msg_code definitions (Hans Zhang)

- Make the cadence core buildable as a module (Kishon Vijay Abraham I)

- Add cdns_pcie_host_disable() and cdns_pcie_ep_disable() for use by
  loadable drivers when they are removed (Siddharth Vadapalli)

- Make j721e buildable as a loadable and removable module (Siddharth
  Vadapalli)

- Fix j721e host/endpoint dependencies that result in link failures in
  some configs (Arnd Bergmann)

* pci/controller/cadence:
  PCI: j721e: Fix host/endpoint dependencies
  PCI: j721e: Add support to build as a loadable module
  PCI: cadence-ep: Introduce cdns_pcie_ep_disable() helper for cleanup
  PCI: cadence-host: Introduce cdns_pcie_host_disable() helper for cleanup
  PCI: cadence: Add support to build pcie-cadence library as a kernel module
  PCI: cadence: Remove duplicate message code definitions
  PCI: cadence: Fix runtime atomic count underflow
parents c3b2f9dc 3c05e884

drivers/pci/controller/cadence/Kconfig

+8 −8
Original line number Diff line number Diff line
@@ -4,16 +4,16 @@ menu "Cadence-based PCIe controllers" 
	depends on PCI



config PCIE_CADENCE

	bool

	tristate



config PCIE_CADENCE_HOST

	bool

	tristate

	depends on OF

	select IRQ_DOMAIN

	select PCIE_CADENCE



config PCIE_CADENCE_EP

	bool

	tristate

	depends on OF

	depends on PCI_ENDPOINT

	select PCIE_CADENCE
@@ -43,13 +43,14 @@ config PCIE_CADENCE_PLAT_EP 
	  different vendors SoCs.



config PCI_J721E

	bool

	tristate

	select PCIE_CADENCE_HOST if PCI_J721E_HOST != n

	select PCIE_CADENCE_EP if PCI_J721E_EP != n



config PCI_J721E_HOST

	bool "TI J721E PCIe controller (host mode)"

	tristate "TI J721E PCIe controller (host mode)"

	depends on ARCH_K3 || COMPILE_TEST

	depends on OF

	select PCIE_CADENCE_HOST

	select PCI_J721E

	help

	  Say Y here if you want to support the TI J721E PCIe platform
@@ -57,11 +58,10 @@ config PCI_J721E_HOST 
	  core.



config PCI_J721E_EP

	bool "TI J721E PCIe controller (endpoint mode)"

	tristate "TI J721E PCIe controller (endpoint mode)"

	depends on ARCH_K3 || COMPILE_TEST

	depends on OF

	depends on PCI_ENDPOINT

	select PCIE_CADENCE_EP

	select PCI_J721E

	help

	  Say Y here if you want to support the TI J721E PCIe platform

drivers/pci/controller/cadence/pci-j721e.c

+31 −3
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ 
#include <linux/irqchip/chained_irq.h>

#include <linux/irqdomain.h>

#include <linux/mfd/syscon.h>

#include <linux/module.h>

#include <linux/of.h>

#include <linux/pci.h>

#include <linux/platform_device.h>
@@ -27,6 +28,7 @@ 
#define cdns_pcie_to_rc(p) container_of(p, struct cdns_pcie_rc, pcie)



#define ENABLE_REG_SYS_2	0x108

#define ENABLE_CLR_REG_SYS_2	0x308

#define STATUS_REG_SYS_2	0x508

#define STATUS_CLR_REG_SYS_2	0x708

#define LINK_DOWN		BIT(1)
@@ -116,6 +118,15 @@ static irqreturn_t j721e_pcie_link_irq_handler(int irq, void *priv) 
	return IRQ_HANDLED;

}



static void j721e_pcie_disable_link_irq(struct j721e_pcie *pcie)

{

	u32 reg;



	reg = j721e_pcie_intd_readl(pcie, ENABLE_CLR_REG_SYS_2);

	reg |= pcie->linkdown_irq_regfield;

	j721e_pcie_intd_writel(pcie, ENABLE_CLR_REG_SYS_2, reg);

}



static void j721e_pcie_config_link_irq(struct j721e_pcie *pcie)

{

	u32 reg;
@@ -464,7 +475,7 @@ static int j721e_pcie_probe(struct platform_device *pdev) 


	switch (mode) {

	case PCI_MODE_RC:

		if (!IS_ENABLED(CONFIG_PCIE_CADENCE_HOST))

		if (!IS_ENABLED(CONFIG_PCI_J721E_HOST))

			return -ENODEV;



		bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc));
@@ -483,7 +494,7 @@ static int j721e_pcie_probe(struct platform_device *pdev) 
		pcie->cdns_pcie = cdns_pcie;

		break;

	case PCI_MODE_EP:

		if (!IS_ENABLED(CONFIG_PCIE_CADENCE_EP))

		if (!IS_ENABLED(CONFIG_PCI_J721E_EP))

			return -ENODEV;



		ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
@@ -633,9 +644,22 @@ static void j721e_pcie_remove(struct platform_device *pdev) 
	struct j721e_pcie *pcie = platform_get_drvdata(pdev);

	struct cdns_pcie *cdns_pcie = pcie->cdns_pcie;

	struct device *dev = &pdev->dev;

	struct cdns_pcie_ep *ep;

	struct cdns_pcie_rc *rc;



	if (pcie->mode == PCI_MODE_RC) {

		rc = container_of(cdns_pcie, struct cdns_pcie_rc, pcie);

		cdns_pcie_host_disable(rc);

	} else {

		ep = container_of(cdns_pcie, struct cdns_pcie_ep, pcie);

		cdns_pcie_ep_disable(ep);

	}



	gpiod_set_value_cansleep(pcie->reset_gpio, 0);



	clk_disable_unprepare(pcie->refclk);

	cdns_pcie_disable_phy(cdns_pcie);

	j721e_pcie_disable_link_irq(pcie);

	pm_runtime_put(dev);

	pm_runtime_disable(dev);

}
@@ -730,4 +754,8 @@ static struct platform_driver j721e_pcie_driver = { 
		.pm	= pm_sleep_ptr(&j721e_pcie_pm_ops),

	},

};

builtin_platform_driver(j721e_pcie_driver);
 
module_platform_driver(j721e_pcie_driver);



MODULE_LICENSE("GPL");

MODULE_DESCRIPTION("PCIe controller driver for TI's J721E and related SoCs");

MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");

drivers/pci/controller/cadence/pcie-cadence-ep.c

+20 −2
Original line number Diff line number Diff line
@@ -6,12 +6,14 @@ 
#include <linux/bitfield.h>

#include <linux/delay.h>

#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/of.h>

#include <linux/pci-epc.h>

#include <linux/platform_device.h>

#include <linux/sizes.h>



#include "pcie-cadence.h"

#include "../../pci.h"



#define CDNS_PCIE_EP_MIN_APERTURE		128	/* 128 bytes */

#define CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE		0x1
@@ -337,10 +339,10 @@ static void cdns_pcie_ep_assert_intx(struct cdns_pcie_ep *ep, u8 fn, u8 intx, 


	if (is_asserted) {

		ep->irq_pending |= BIT(intx);

		msg_code = MSG_CODE_ASSERT_INTA + intx;

		msg_code = PCIE_MSG_CODE_ASSERT_INTA + intx;

	} else {

		ep->irq_pending &= ~BIT(intx);

		msg_code = MSG_CODE_DEASSERT_INTA + intx;

		msg_code = PCIE_MSG_CODE_DEASSERT_INTA + intx;

	}



	spin_lock_irqsave(&ep->lock, flags);
@@ -644,6 +646,17 @@ static const struct pci_epc_ops cdns_pcie_epc_ops = { 
	.get_features	= cdns_pcie_ep_get_features,

};



void cdns_pcie_ep_disable(struct cdns_pcie_ep *ep)

{

	struct device *dev = ep->pcie.dev;

	struct pci_epc *epc = to_pci_epc(dev);



	pci_epc_deinit_notify(epc);

	pci_epc_mem_free_addr(epc, ep->irq_phys_addr, ep->irq_cpu_addr,

			      SZ_128K);

	pci_epc_mem_exit(epc);

}

EXPORT_SYMBOL_GPL(cdns_pcie_ep_disable);



int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep)

{
@@ -751,3 +764,8 @@ int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep) 


	return ret;

}

EXPORT_SYMBOL_GPL(cdns_pcie_ep_setup);



MODULE_LICENSE("GPL");

MODULE_DESCRIPTION("Cadence PCIe endpoint controller driver");

MODULE_AUTHOR("Cyrille Pitchen <cyrille.pitchen@free-electrons.com>");

drivers/pci/controller/cadence/pcie-cadence-host.c

+114 −10
Original line number Diff line number Diff line
@@ -5,6 +5,7 @@ 


#include <linux/delay.h>

#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/list_sort.h>

#include <linux/of_address.h>

#include <linux/of_pci.h>
@@ -72,6 +73,7 @@ void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn, 


	return rc->cfg_base + (where & 0xfff);

}

EXPORT_SYMBOL_GPL(cdns_pci_map_bus);



static struct pci_ops cdns_pcie_host_ops = {

	.map_bus	= cdns_pci_map_bus,
@@ -150,6 +152,14 @@ static int cdns_pcie_retrain(struct cdns_pcie *pcie) 
	return ret;

}



static void cdns_pcie_host_disable_ptm_response(struct cdns_pcie *pcie)

{

	u32 val;



	val = cdns_pcie_readl(pcie, CDNS_PCIE_LM_PTM_CTRL);

	cdns_pcie_writel(pcie, CDNS_PCIE_LM_PTM_CTRL, val & ~CDNS_PCIE_LM_TPM_CTRL_PTMRSEN);

}



static void cdns_pcie_host_enable_ptm_response(struct cdns_pcie *pcie)

{

	u32 val;
@@ -175,6 +185,26 @@ static int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc) 
	return ret;

}



static void cdns_pcie_host_deinit_root_port(struct cdns_pcie_rc *rc)

{

	struct cdns_pcie *pcie = &rc->pcie;

	u32 value, ctrl;



	cdns_pcie_rp_writew(pcie, PCI_CLASS_DEVICE, 0xffff);

	cdns_pcie_rp_writeb(pcie, PCI_CLASS_PROG, 0xff);

	cdns_pcie_rp_writeb(pcie, PCI_CLASS_REVISION, 0xff);

	cdns_pcie_writel(pcie, CDNS_PCIE_LM_ID, 0xffffffff);

	cdns_pcie_rp_writew(pcie, PCI_DEVICE_ID, 0xffff);

	ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED;

	value = ~(CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(ctrl) |

		CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(ctrl) |

		CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE |

		CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS |

		CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE |

		CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS);

	cdns_pcie_writel(pcie, CDNS_PCIE_LM_RC_BAR_CFG, value);

}



static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc)

{

	struct cdns_pcie *pcie = &rc->pcie;
@@ -391,6 +421,32 @@ static int cdns_pcie_host_dma_ranges_cmp(void *priv, const struct list_head *a, 
        return resource_size(entry2->res) - resource_size(entry1->res);

}



static void cdns_pcie_host_unmap_dma_ranges(struct cdns_pcie_rc *rc)

{

	struct cdns_pcie *pcie = &rc->pcie;

	enum cdns_pcie_rp_bar bar;

	u32 value;



	/* Reset inbound configuration for all BARs which were being used */

	for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++) {

		if (rc->avail_ib_bar[bar])

			continue;



		cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar), 0);

		cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar), 0);



		if (bar == RP_NO_BAR)

			continue;



		value = ~(LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) |

			  LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) |

			  LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) |

			  LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) |

			  LM_RC_BAR_CFG_APERTURE(bar, bar_aperture_mask[bar] + 2));

		cdns_pcie_writel(pcie, CDNS_PCIE_LM_RC_BAR_CFG, value);

	}

}



static int cdns_pcie_host_map_dma_ranges(struct cdns_pcie_rc *rc)

{

	struct cdns_pcie *pcie = &rc->pcie;
@@ -428,6 +484,29 @@ static int cdns_pcie_host_map_dma_ranges(struct cdns_pcie_rc *rc) 
	return 0;

}



static void cdns_pcie_host_deinit_address_translation(struct cdns_pcie_rc *rc)

{

	struct cdns_pcie *pcie = &rc->pcie;

	struct pci_host_bridge *bridge = pci_host_bridge_from_priv(rc);

	struct resource_entry *entry;

	int r;



	cdns_pcie_host_unmap_dma_ranges(rc);



	/*

	 * Reset outbound region 0 which was reserved for configuration space

	 * accesses.

	 */

	cdns_pcie_reset_outbound_region(pcie, 0);



	/* Reset rest of the outbound regions */

	r = 1;

	resource_list_for_each_entry(entry, &bridge->windows) {

		cdns_pcie_reset_outbound_region(pcie, r);

		r++;

	}

}



static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc)

{

	struct cdns_pcie *pcie = &rc->pcie;
@@ -485,6 +564,12 @@ static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc) 
	return cdns_pcie_host_map_dma_ranges(rc);

}



static void cdns_pcie_host_deinit(struct cdns_pcie_rc *rc)

{

	cdns_pcie_host_deinit_address_translation(rc);

	cdns_pcie_host_deinit_root_port(rc);

}



int cdns_pcie_host_init(struct cdns_pcie_rc *rc)

{

	int err;
@@ -495,6 +580,15 @@ int cdns_pcie_host_init(struct cdns_pcie_rc *rc) 


	return cdns_pcie_host_init_address_translation(rc);

}

EXPORT_SYMBOL_GPL(cdns_pcie_host_init);



static void cdns_pcie_host_link_disable(struct cdns_pcie_rc *rc)

{

	struct cdns_pcie *pcie = &rc->pcie;



	cdns_pcie_stop_link(pcie);

	cdns_pcie_host_disable_ptm_response(pcie);

}



int cdns_pcie_host_link_setup(struct cdns_pcie_rc *rc)

{
@@ -519,6 +613,20 @@ int cdns_pcie_host_link_setup(struct cdns_pcie_rc *rc) 


	return 0;

}

EXPORT_SYMBOL_GPL(cdns_pcie_host_link_setup);



void cdns_pcie_host_disable(struct cdns_pcie_rc *rc)

{

	struct pci_host_bridge *bridge;



	bridge = pci_host_bridge_from_priv(rc);

	pci_stop_root_bus(bridge->bus);

	pci_remove_root_bus(bridge->bus);



	cdns_pcie_host_deinit(rc);

	cdns_pcie_host_link_disable(rc);

}

EXPORT_SYMBOL_GPL(cdns_pcie_host_disable);



int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)

{
@@ -570,14 +678,10 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) 
	if (!bridge->ops)

		bridge->ops = &cdns_pcie_host_ops;



	ret = pci_host_probe(bridge);

	if (ret < 0)

		goto err_init;



	return 0;



 err_init:

	pm_runtime_put_sync(dev);



	return ret;

	return pci_host_probe(bridge);

}

EXPORT_SYMBOL_GPL(cdns_pcie_host_setup);



MODULE_LICENSE("GPL");

MODULE_DESCRIPTION("Cadence PCIe host controller driver");

MODULE_AUTHOR("Cyrille Pitchen <cyrille.pitchen@free-electrons.com>");

drivers/pci/controller/cadence/pcie-cadence.c

+12 −0
Original line number Diff line number Diff line
@@ -4,6 +4,7 @@ 
// Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>



#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/of.h>



#include "pcie-cadence.h"
@@ -23,6 +24,7 @@ void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie) 


	cdns_pcie_writel(pcie, CDNS_PCIE_LTSSM_CONTROL_CAP, ltssm_control_cap);

}

EXPORT_SYMBOL_GPL(cdns_pcie_detect_quiet_min_delay_set);



void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn,

				   u32 r, bool is_io,
@@ -100,6 +102,7 @@ void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, 
	cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r), addr0);

	cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r), addr1);

}

EXPORT_SYMBOL_GPL(cdns_pcie_set_outbound_region);



void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie,

						  u8 busnr, u8 fn,
@@ -134,6 +137,7 @@ void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, 
	cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r), addr0);

	cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r), addr1);

}

EXPORT_SYMBOL_GPL(cdns_pcie_set_outbound_region_for_normal_msg);



void cdns_pcie_reset_outbound_region(struct cdns_pcie *pcie, u32 r)

{
@@ -146,6 +150,7 @@ void cdns_pcie_reset_outbound_region(struct cdns_pcie *pcie, u32 r) 
	cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r), 0);

	cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r), 0);

}

EXPORT_SYMBOL_GPL(cdns_pcie_reset_outbound_region);



void cdns_pcie_disable_phy(struct cdns_pcie *pcie)

{
@@ -156,6 +161,7 @@ void cdns_pcie_disable_phy(struct cdns_pcie *pcie) 
		phy_exit(pcie->phy[i]);

	}

}

EXPORT_SYMBOL_GPL(cdns_pcie_disable_phy);



int cdns_pcie_enable_phy(struct cdns_pcie *pcie)

{
@@ -184,6 +190,7 @@ int cdns_pcie_enable_phy(struct cdns_pcie *pcie) 


	return ret;

}

EXPORT_SYMBOL_GPL(cdns_pcie_enable_phy);



int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie)

{
@@ -243,6 +250,7 @@ int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie) 


	return ret;

}

EXPORT_SYMBOL_GPL(cdns_pcie_init_phy);



static int cdns_pcie_suspend_noirq(struct device *dev)

{
@@ -271,3 +279,7 @@ const struct dev_pm_ops cdns_pcie_pm_ops = { 
	NOIRQ_SYSTEM_SLEEP_PM_OPS(cdns_pcie_suspend_noirq,

				  cdns_pcie_resume_noirq)

};



MODULE_LICENSE("GPL");

MODULE_DESCRIPTION("Cadence PCIe controller driver");

MODULE_AUTHOR("Cyrille Pitchen <cyrille.pitchen@free-electrons.com>");