Commit 3f5b8f7f authored by Li Ming's avatar Li Ming Committed by Dave Jiang
Browse files

cxl/port: Remove devm_cxl_port_enumerate_dports()



devm_cxl_port_enumerate_dports() is not longer used after below commit
commit 4f06d81e ("cxl: Defer dport allocation for switch ports")

Delete it and the relevant interface implemented in cxl_test.

Signed-off-by: default avatarLi Ming <ming.li@zohomail.com>
Reviewed-by: default avatarDave Jiang <dave.jiang@intel.com>
Reviewed-by: default avatarJonathan Cameron <jonathan.cameron@huawei.com>
Signed-off-by: default avatarDave Jiang <dave.jiang@intel.com>
parent 82b5d7e3
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+8 −79
Original line number Diff line number Diff line
@@ -71,85 +71,6 @@ struct cxl_dport *__devm_cxl_add_dport_by_dev(struct cxl_port *port,
}
EXPORT_SYMBOL_NS_GPL(__devm_cxl_add_dport_by_dev, "CXL");

struct cxl_walk_context {
	struct pci_bus *bus;
	struct cxl_port *port;
	int type;
	int error;
	int count;
};

static int match_add_dports(struct pci_dev *pdev, void *data)
{
	struct cxl_walk_context *ctx = data;
	struct cxl_port *port = ctx->port;
	int type = pci_pcie_type(pdev);
	struct cxl_register_map map;
	struct cxl_dport *dport;
	u32 lnkcap, port_num;
	int rc;

	if (pdev->bus != ctx->bus)
		return 0;
	if (!pci_is_pcie(pdev))
		return 0;
	if (type != ctx->type)
		return 0;
	if (pci_read_config_dword(pdev, pci_pcie_cap(pdev) + PCI_EXP_LNKCAP,
				  &lnkcap))
		return 0;

	rc = cxl_find_regblock(pdev, CXL_REGLOC_RBI_COMPONENT, &map);
	if (rc)
		dev_dbg(&port->dev, "failed to find component registers\n");

	port_num = FIELD_GET(PCI_EXP_LNKCAP_PN, lnkcap);
	dport = devm_cxl_add_dport(port, &pdev->dev, port_num, map.resource);
	if (IS_ERR(dport)) {
		ctx->error = PTR_ERR(dport);
		return PTR_ERR(dport);
	}
	ctx->count++;

	return 0;
}

/**
 * devm_cxl_port_enumerate_dports - enumerate downstream ports of the upstream port
 * @port: cxl_port whose ->uport_dev is the upstream of dports to be enumerated
 *
 * Returns a positive number of dports enumerated or a negative error
 * code.
 */
int devm_cxl_port_enumerate_dports(struct cxl_port *port)
{
	struct pci_bus *bus = cxl_port_to_pci_bus(port);
	struct cxl_walk_context ctx;
	int type;

	if (!bus)
		return -ENXIO;

	if (pci_is_root_bus(bus))
		type = PCI_EXP_TYPE_ROOT_PORT;
	else
		type = PCI_EXP_TYPE_DOWNSTREAM;

	ctx = (struct cxl_walk_context) {
		.port = port,
		.bus = bus,
		.type = type,
	};
	pci_walk_bus(bus, match_add_dports, &ctx);

	if (ctx.count == 0)
		return -ENODEV;
	if (ctx.error)
		return ctx.error;
	return ctx.count;
}
EXPORT_SYMBOL_NS_GPL(devm_cxl_port_enumerate_dports, "CXL");

static int cxl_dvsec_mem_range_valid(struct cxl_dev_state *cxlds, int id)
{
	struct pci_dev *pdev = to_pci_dev(cxlds->dev);
@@ -1217,6 +1138,14 @@ int cxl_gpf_port_setup(struct cxl_dport *dport)
	return 0;
}

struct cxl_walk_context {
	struct pci_bus *bus;
	struct cxl_port *port;
	int type;
	int error;
	int count;
};

static int count_dports(struct pci_dev *pdev, void *data)
{
	struct cxl_walk_context *ctx = data;
+0 −1
Original line number Diff line number Diff line
@@ -127,7 +127,6 @@ static inline bool cxl_pci_flit_256(struct pci_dev *pdev)
	return lnksta2 & PCI_EXP_LNKSTA2_FLIT;
}

int devm_cxl_port_enumerate_dports(struct cxl_port *port);
struct cxl_dev_state;
void read_cdat_data(struct cxl_port *port);
void cxl_cor_error_detected(struct pci_dev *pdev);
+0 −1
Original line number Diff line number Diff line
@@ -4,7 +4,6 @@ ldflags-y += --wrap=is_acpi_device_node
ldflags-y += --wrap=acpi_evaluate_integer
ldflags-y += --wrap=acpi_pci_find_root
ldflags-y += --wrap=nvdimm_bus_register
ldflags-y += --wrap=devm_cxl_port_enumerate_dports
ldflags-y += --wrap=cxl_await_media_ready
ldflags-y += --wrap=devm_cxl_add_rch_dport
ldflags-y += --wrap=cxl_rcd_component_reg_phys
+0 −32
Original line number Diff line number Diff line
@@ -995,37 +995,6 @@ static int get_port_array(struct cxl_port *port,
	return 0;
}

static int mock_cxl_port_enumerate_dports(struct cxl_port *port)
{
	struct platform_device **array;
	int i, array_size;
	int rc;

	rc = get_port_array(port, &array, &array_size);
	if (rc)
		return rc;

	for (i = 0; i < array_size; i++) {
		struct platform_device *pdev = array[i];
		struct cxl_dport *dport;

		if (pdev->dev.parent != port->uport_dev) {
			dev_dbg(&port->dev, "%s: mismatch parent %s\n",
				dev_name(port->uport_dev),
				dev_name(pdev->dev.parent));
			continue;
		}

		dport = devm_cxl_add_dport(port, &pdev->dev, pdev->id,
					   CXL_RESOURCE_NONE);

		if (IS_ERR(dport))
			return PTR_ERR(dport);
	}

	return 0;
}

static struct cxl_dport *mock_cxl_add_dport_by_dev(struct cxl_port *port,
						   struct device *dport_dev)
{
@@ -1114,7 +1083,6 @@ static struct cxl_mock_ops cxl_mock_ops = {
	.acpi_pci_find_root = mock_acpi_pci_find_root,
	.devm_cxl_switch_port_decoders_setup = mock_cxl_switch_port_decoders_setup,
	.devm_cxl_endpoint_decoders_setup = mock_cxl_endpoint_decoders_setup,
	.devm_cxl_port_enumerate_dports = mock_cxl_port_enumerate_dports,
	.cxl_endpoint_parse_cdat = mock_cxl_endpoint_parse_cdat,
	.devm_cxl_add_dport_by_dev = mock_cxl_add_dport_by_dev,
	.list = LIST_HEAD_INIT(cxl_mock_ops.list),
+0 −15
Original line number Diff line number Diff line
@@ -172,21 +172,6 @@ int __wrap_devm_cxl_endpoint_decoders_setup(struct cxl_port *port)
}
EXPORT_SYMBOL_NS_GPL(__wrap_devm_cxl_endpoint_decoders_setup, "CXL");

int __wrap_devm_cxl_port_enumerate_dports(struct cxl_port *port)
{
	int rc, index;
	struct cxl_mock_ops *ops = get_cxl_mock_ops(&index);

	if (ops && ops->is_mock_port(port->uport_dev))
		rc = ops->devm_cxl_port_enumerate_dports(port);
	else
		rc = devm_cxl_port_enumerate_dports(port);
	put_cxl_mock_ops(index);

	return rc;
}
EXPORT_SYMBOL_NS_GPL(__wrap_devm_cxl_port_enumerate_dports, "CXL");

int __wrap_cxl_await_media_ready(struct cxl_dev_state *cxlds)
{
	int rc, index;
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