Commit 3f887edd authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'phy-for-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy 

Pull phy updates from Vinod Koul:
 "New Support:
   - Qualcomm Eliza QMP UFS PHY
   - Canaan K230 USB 2.0 PHY driver
   - Mediatek mt8167 dsi-phy
   - Eswin EIC7700 SATA PHY driver

  Updates:
   - Sorted subsytem Makefile/Kconfig and some kernel-doc udpates"

* tag 'phy-for-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy:
  dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: document the Eliza QMP UFS PHY
  phy: qcom: m31-eusb2: clear PLL_EN during init
  phy: eswin: Create eswin directory and add EIC7700 SATA PHY driver
  dt-bindings: phy: eswin: Document the EIC7700 SoC SATA PHY
  phy: apple: apple: Use local variable for ioremap return value
  phy: qcom: qmp-usbc: Simplify check for non-NULL pointer
  phy: marvell: mmp3-hsic: Avoid re-casting __iomem
  phy: apple: atc: Make atcphy_dwc3_reset_ops variable static
  dt-bindings: phy: mediatek,dsi-phy: Add support for mt8167
  phy: usb: Add driver for Canaan K230 USB 2.0 PHY
  dt-bindings: phy: Add Canaan K230 USB PHY
  phy: phy-mtk-tphy: Update names and format of kernel-doc comments
  phy: Sort the subsystem Kconfig
  phy: Sort the subsystem Makefile
  phy: move spacemit pcie driver to its subfolder
parents 65bec0c4 caf08514

Documentation/devicetree/bindings/phy/canaan,k230-usb-phy.yaml

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+35 −0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/phy/canaan,k230-usb-phy.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Canaan K230 USB2.0 PHY



maintainers:

  - Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>



properties:

  compatible:

    const: canaan,k230-usb-phy



  reg:

    maxItems: 1



  "#phy-cells":

    const: 1



required:

  - compatible

  - reg

  - "#phy-cells"



additionalProperties: false



examples:

  - |

    usbphy: usb-phy@91585000 {

        compatible = "canaan,k230-usb-phy";

        reg = <0x91585000 0x400>;

        #phy-cells = <1>;

    };

Documentation/devicetree/bindings/phy/eswin,eic7700-sata-phy.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/phy/eswin,eic7700-sata-phy.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Eswin EIC7700 SoC SATA PHY



maintainers:

  - Yulin Lu <luyulin@eswincomputing.com>

  - Huan He <hehuan1@eswincomputing.com>



properties:

  compatible:

    const: eswin,eic7700-sata-phy



  reg:

    maxItems: 1



  clocks:

    maxItems: 1



  clock-names:

    const: phy



  resets:

    maxItems: 2



  reset-names:

    items:

      - const: port

      - const: phy



  eswin,tx-amplitude-tuning:

    description: This adjusts the transmitter amplitude signal, and its value

      is derived from eye diagram tuning. The three values correspond to Gen1,

      Gen2, and Gen3 parameters respectively.

    $ref: /schemas/types.yaml#/definitions/uint32-array

    items:

      - description: Gen1 parameter.

        minimum: 0

        maximum: 0x7f

      - description: Gen2 parameter.

        minimum: 0

        maximum: 0x7f

      - description: Gen3 parameter.

        minimum: 0

        maximum: 0x7f

    default: [0, 0, 0]



  eswin,tx-preemph-tuning:

    description: This adjusts the transmitter de-emphasis signal, and its value

      is derived from eye diagram tuning. The three values correspond to Gen1,

      Gen2, and Gen3 parameters respectively.

    $ref: /schemas/types.yaml#/definitions/uint32-array

    items:

      - description: Gen1 parameter.

        minimum: 0

        maximum: 0x3f

      - description: Gen2 parameter.

        minimum: 0

        maximum: 0x3f

      - description: Gen3 parameter.

        minimum: 0

        maximum: 0x3f

    default: [0, 0, 0]



  "#phy-cells":

    const: 0



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - resets

  - reset-names

  - "#phy-cells"



additionalProperties: false



examples:

  - |

    sata-phy@50440300 {

        compatible = "eswin,eic7700-sata-phy";

        reg = <0x50440300 0x40>;

        clocks = <&hspcrg 17>;

        clock-names = "phy";

        resets = <&hspcrg 0>, <&hspcrg 1>;

        reset-names = "port", "phy";

        #phy-cells = <0>;

    };

Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml

+6 −2
Original line number Diff line number Diff line
@@ -16,6 +16,10 @@ description: 
properties:

  compatible:

    oneOf:

      - items:

          - enum:

              - qcom,qcs8300-qmp-ufs-phy

          - const: qcom,sa8775p-qmp-ufs-phy

      - items:

          - enum:

              - qcom,qcs615-qmp-ufs-phy
@@ -26,8 +30,8 @@ properties: 
          - const: qcom,sm8550-qmp-ufs-phy

      - items:

          - enum:

              - qcom,qcs8300-qmp-ufs-phy

          - const: qcom,sa8775p-qmp-ufs-phy

              - qcom,eliza-qmp-ufs-phy

          - const: qcom,sm8650-qmp-ufs-phy

      - items:

          - enum:

              - qcom,kaanapali-qmp-ufs-phy

drivers/phy/Kconfig

+46 −56
Original line number Diff line number Diff line
@@ -46,6 +46,26 @@ config GENERIC_PHY_MIPI_DPHY 
	  Provides a number of helpers a core functions for MIPI D-PHY

	  drivers to us.



config PHY_AIROHA_PCIE

	tristate "Airoha PCIe-PHY Driver"

	depends on ARCH_AIROHA || COMPILE_TEST

	depends on OF

	select GENERIC_PHY

	help

	  Say Y here to add support for Airoha PCIe PHY driver.

	  This driver create the basic PHY instance and provides initialize

	  callback for PCIe GEN3 port.



config PHY_CAN_TRANSCEIVER

	tristate "CAN transceiver PHY"

	select GENERIC_PHY

	select MULTIPLEXER

	help

	  This option enables support for CAN transceivers as a PHY. This

	  driver provides function for putting the transceivers in various

	  functional modes using gpios and sets the attribute max link

	  rate, for CAN drivers.



config PHY_GOOGLE_USB

	tristate "Google Tensor SoC USB PHY driver"

	select GENERIC_PHY
@@ -57,6 +77,18 @@ config PHY_GOOGLE_USB 
	  both of which are integrated with the DWC3 USB DRD controller.

	  This driver currently supports USB high-speed.



config USB_LGM_PHY

	tristate "INTEL Lightning Mountain USB PHY Driver"

	depends on USB_SUPPORT

	depends on X86 || COMPILE_TEST

	select USB_PHY

	select REGULATOR

	select REGULATOR_FIXED_VOLTAGE

	help

	  Enable this to support Intel DWC3 PHY USB phy. This driver provides

	  interface to interact with USB GEN-II and USB 3.x PHY that is part

	  of the Intel network SOC.



config PHY_LPC18XX_USB_OTG

	tristate "NXP LPC18xx/43xx SoC USB OTG PHY driver"

	depends on OF && (ARCH_LPC18XX || COMPILE_TEST)
@@ -68,6 +100,17 @@ config PHY_LPC18XX_USB_OTG 
	  This driver is need for USB0 support on LPC18xx/43xx and takes

	  care of enabling and clock setup.



config PHY_NXP_PTN3222

	tristate "NXP PTN3222 1-port eUSB2 to USB2 redriver"

	depends on I2C

	depends on OF

	select GENERIC_PHY

	help

	  Enable this to support NXP PTN3222 1-port eUSB2 to USB2 Redriver.

	  This redriver performs translation between eUSB2 and USB2 signalling

	  schemes. It supports all three USB 2.0 data rates: Low Speed, Full

	  Speed and High Speed.



config PHY_PISTACHIO_USB

	tristate "IMG Pistachio USB2.0 PHY driver"

	depends on MIPS || COMPILE_TEST
@@ -90,69 +133,17 @@ config PHY_XGENE 
	help

	  This option enables support for APM X-Gene SoC multi-purpose PHY.



config USB_LGM_PHY

	tristate "INTEL Lightning Mountain USB PHY Driver"

	depends on USB_SUPPORT

	depends on X86 || COMPILE_TEST

	select USB_PHY

	select REGULATOR

	select REGULATOR_FIXED_VOLTAGE

	help

	  Enable this to support Intel DWC3 PHY USB phy. This driver provides

	  interface to interact with USB GEN-II and USB 3.x PHY that is part

	  of the Intel network SOC.



config PHY_CAN_TRANSCEIVER

	tristate "CAN transceiver PHY"

	select GENERIC_PHY

	select MULTIPLEXER

	help

	  This option enables support for CAN transceivers as a PHY. This

	  driver provides function for putting the transceivers in various

	  functional modes using gpios and sets the attribute max link

	  rate, for CAN drivers.



config PHY_AIROHA_PCIE

	tristate "Airoha PCIe-PHY Driver"

	depends on ARCH_AIROHA || COMPILE_TEST

	depends on OF

	select GENERIC_PHY

	help

	  Say Y here to add support for Airoha PCIe PHY driver.

	  This driver create the basic PHY instance and provides initialize

	  callback for PCIe GEN3 port.



config PHY_NXP_PTN3222

	tristate "NXP PTN3222 1-port eUSB2 to USB2 redriver"

	depends on I2C

	depends on OF

	select GENERIC_PHY

	help

	  Enable this to support NXP PTN3222 1-port eUSB2 to USB2 Redriver.

	  This redriver performs translation between eUSB2 and USB2 signalling

	  schemes. It supports all three USB 2.0 data rates: Low Speed, Full

	  Speed and High Speed.



config PHY_SPACEMIT_K1_PCIE

	tristate "PCIe and combo PHY driver for the SpacemiT K1 SoC"

	depends on ARCH_SPACEMIT || COMPILE_TEST

	depends on COMMON_CLK

	depends on HAS_IOMEM

	depends on OF

	select GENERIC_PHY

	default ARCH_SPACEMIT

	help

	  Enable support for the PCIe and USB 3 combo PHY and two

	  PCIe-only PHYs used in the SpacemiT K1 SoC.



source "drivers/phy/allwinner/Kconfig"

source "drivers/phy/amlogic/Kconfig"

source "drivers/phy/apple/Kconfig"

source "drivers/phy/broadcom/Kconfig"

source "drivers/phy/cadence/Kconfig"

source "drivers/phy/canaan/Kconfig"

source "drivers/phy/eswin/Kconfig"

source "drivers/phy/freescale/Kconfig"

source "drivers/phy/hisilicon/Kconfig"

source "drivers/phy/ingenic/Kconfig"

source "drivers/phy/intel/Kconfig"

source "drivers/phy/lantiq/Kconfig"

source "drivers/phy/marvell/Kconfig"

source "drivers/phy/mediatek/Kconfig"
@@ -174,7 +165,6 @@ source "drivers/phy/starfive/Kconfig" 
source "drivers/phy/sunplus/Kconfig"

source "drivers/phy/tegra/Kconfig"

source "drivers/phy/ti/Kconfig"

source "drivers/phy/intel/Kconfig"

source "drivers/phy/xilinx/Kconfig"



endmenu

drivers/phy/Makefile

+7 −5
Original line number Diff line number Diff line
@@ -7,21 +7,23 @@ obj-$(CONFIG_PHY_COMMON_PROPS) += phy-common-props.o 
obj-$(CONFIG_PHY_COMMON_PROPS_TEST)	+= phy-common-props-test.o

obj-$(CONFIG_GENERIC_PHY)		+= phy-core.o

obj-$(CONFIG_GENERIC_PHY_MIPI_DPHY)	+= phy-core-mipi-dphy.o

obj-$(CONFIG_PHY_AIROHA_PCIE)		+= phy-airoha-pcie.o

obj-$(CONFIG_PHY_CAN_TRANSCEIVER)	+= phy-can-transceiver.o

obj-$(CONFIG_PHY_GOOGLE_USB)		+= phy-google-usb.o

obj-$(CONFIG_USB_LGM_PHY)		+= phy-lgm-usb.o

obj-$(CONFIG_PHY_LPC18XX_USB_OTG)	+= phy-lpc18xx-usb-otg.o

obj-$(CONFIG_PHY_XGENE)			+= phy-xgene.o

obj-$(CONFIG_PHY_NXP_PTN3222)		+= phy-nxp-ptn3222.o

obj-$(CONFIG_PHY_PISTACHIO_USB)		+= phy-pistachio-usb.o

obj-$(CONFIG_PHY_SNPS_EUSB2)		+= phy-snps-eusb2.o

obj-$(CONFIG_USB_LGM_PHY)		+= phy-lgm-usb.o

obj-$(CONFIG_PHY_AIROHA_PCIE)		+= phy-airoha-pcie.o

obj-$(CONFIG_PHY_NXP_PTN3222)		+= phy-nxp-ptn3222.o

obj-$(CONFIG_PHY_SPACEMIT_K1_PCIE)	+= phy-spacemit-k1-pcie.o

obj-$(CONFIG_PHY_XGENE)			+= phy-xgene.o



obj-$(CONFIG_GENERIC_PHY)		+= allwinner/	\

					   amlogic/	\

					   apple/	\

					   broadcom/	\

					   cadence/	\

					   canaan/	\

					   eswin/	\

					   freescale/	\

					   hisilicon/	\

					   ingenic/	\