Commit 402377bb authored by Matt Roper's avatar Matt Roper Committed by Lucas De Marchi
Browse files

drm/xe/cri: Setup MOCS table 



CRI has a new MOCS table, but uses the same general ops as other Xe2/Xe3
platforms.

Bspec: 71582
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarBalasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Link: https://patch.msgid.link/20251021-cri-v1-3-bf11e61d9f49@intel.com


Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
parent 5e0de2df

drivers/gpu/drm/xe/xe_mocs.c

+26 −0
Original line number Diff line number Diff line
@@ -568,6 +568,23 @@ static const struct xe_mocs_ops xe2_mocs_ops = { 
	.dump = xe2_mocs_dump,

};



/*

 * Note that the "L3" and "L4" register fields actually control the L2 and L3

 * caches respectively on this platform.

 */

static const struct xe_mocs_entry xe3p_xpc_mocs_table[] = {

	/* Defer to PAT */

	MOCS_ENTRY(0, XE2_L3_0_WB | L4_3_UC, 0),

	/* UC */

	MOCS_ENTRY(1, IG_PAT | XE2_L3_3_UC | L4_3_UC, 0),

	/* L2 */

	MOCS_ENTRY(2, IG_PAT | XE2_L3_0_WB | L4_3_UC, 0),

	/* L3 */

	MOCS_ENTRY(3, IG_PAT | XE2_L3_3_UC | L4_0_WB, 0),

	/* L2 + L3 */

	MOCS_ENTRY(4, IG_PAT | XE2_L3_0_WB | L4_0_WB, 0),

};



static unsigned int get_mocs_settings(struct xe_device *xe,

				      struct xe_mocs_info *info)

{
@@ -576,6 +593,15 @@ static unsigned int get_mocs_settings(struct xe_device *xe, 
	memset(info, 0, sizeof(struct xe_mocs_info));



	switch (xe->info.platform) {

	case XE_CRESCENTISLAND:

		info->ops = &xe2_mocs_ops;

		info->table_size = ARRAY_SIZE(xe3p_xpc_mocs_table);

		info->table = xe3p_xpc_mocs_table;

		info->num_mocs_regs = XE2_NUM_MOCS_ENTRIES;

		info->uc_index = 1;

		info->wb_index = 4;

		info->unused_entries_index = 4;

		break;

	case XE_NOVALAKE_S:

	case XE_PANTHERLAKE:

	case XE_LUNARLAKE: