dt-bindings: display/msm: Document MDSS on SA8775P

# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/display/msm/qcom,sa8775p-mdss.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. SA87755P Display MDSS

maintainers:

  - Mahadevan <quic_mahap@quicinc.com>

description:

  SA8775P MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like

  DPU display controller, DP interfaces and EDP etc.

$ref: /schemas/display/msm/mdss-common.yaml#

properties:

  compatible:

    const: qcom,sa8775p-mdss

  clocks:

    items:

      - description: Display AHB

      - description: Display hf AXI

      - description: Display core

  iommus:

    maxItems: 1

  interconnects:

    maxItems: 3

  interconnect-names:

    maxItems: 3

patternProperties:

  "^display-controller@[0-9a-f]+$":

    type: object

    additionalProperties: true

    properties:

      compatible:

        const: qcom,sa8775p-dpu

  "^displayport-controller@[0-9a-f]+$":

    type: object

    additionalProperties: true

    properties:

      compatible:

        items:

          - const: qcom,sa8775p-dp

required:

  - compatible

unevaluatedProperties: false

examples:

  - |

    #include <dt-bindings/interconnect/qcom,icc.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/clock/qcom,sa8775p-gcc.h>

    #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>

    #include <dt-bindings/power/qcom,rpmhpd.h>

    #include <dt-bindings/power/qcom-rpmpd.h>

    display-subsystem@ae00000 {

        compatible = "qcom,sa8775p-mdss";

        reg = <0x0ae00000 0x1000>;

        reg-names = "mdss";

        interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>,

                        <&mmss_noc MASTER_MDP1 &mc_virt SLAVE_EBI1>,

                        <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>;

        interconnect-names = "mdp0-mem",

                             "mdp1-mem",

                             "cpu-cfg";

        resets = <&dispcc_core_bcr>;

        power-domains = <&dispcc_gdsc>;

        clocks = <&dispcc_ahb_clk>,

                 <&gcc GCC_DISP_HF_AXI_CLK>,

                 <&dispcc_mdp_clk>;

        interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;

        interrupt-controller;

        #interrupt-cells = <1>;

        iommus = <&apps_smmu 0x1000 0x402>;

        #address-cells = <1>;

        #size-cells = <1>;

        ranges;

        display-controller@ae01000 {

            compatible = "qcom,sa8775p-dpu";

            reg = <0x0ae01000 0x8f000>,

                  <0x0aeb0000 0x2008>;

            reg-names = "mdp", "vbif";

            clocks = <&gcc GCC_DISP_HF_AXI_CLK>,

                     <&dispcc_ahb_clk>,

                     <&dispcc_mdp_lut_clk>,

                     <&dispcc_mdp_clk>,

                     <&dispcc_mdp_vsync_clk>;

            clock-names = "nrt_bus",

                          "iface",

                          "lut",

                          "core",

                          "vsync";

            assigned-clocks = <&dispcc_mdp_vsync_clk>;

            assigned-clock-rates = <19200000>;

            operating-points-v2 = <&mdss0_mdp_opp_table>;

            power-domains = <&rpmhpd RPMHPD_MMCX>;

            interrupt-parent = <&mdss0>;

            interrupts = <0>;

            ports {

                #address-cells = <1>;

                #size-cells = <0>;

                port@0 {

                    reg = <0>;

                    dpu_intf0_out: endpoint {

                         remote-endpoint = <&mdss0_dp0_in>;

                    };

                };

            };

            mdss0_mdp_opp_table: opp-table {

                compatible = "operating-points-v2";

                opp-375000000 {

                    opp-hz = /bits/ 64 <375000000>;

                    required-opps = <&rpmhpd_opp_svs_l1>;

                };

                opp-500000000 {

                    opp-hz = /bits/ 64 <500000000>;

                    required-opps = <&rpmhpd_opp_nom>;

                };

                opp-575000000 {

                    opp-hz = /bits/ 64 <575000000>;

                    required-opps = <&rpmhpd_opp_turbo>;

                };

                opp-650000000 {

                    opp-hz = /bits/ 64 <650000000>;

                    required-opps = <&rpmhpd_opp_turbo_l1>;

                };

            };

        };

        displayport-controller@af54000 {

            compatible = "qcom,sa8775p-dp";

            pinctrl-0 = <&dp_hot_plug_det>;

            pinctrl-names = "default";

            reg = <0xaf54000 0x104>,

                  <0xaf54200 0x0c0>,

                  <0xaf55000 0x770>,

                  <0xaf56000 0x09c>;

            interrupt-parent = <&mdss0>;

            interrupts = <12>;

            clocks = <&dispcc_mdss_ahb_clk>,

                     <&dispcc_dptx0_aux_clk>,

                     <&dispcc_dptx0_link_clk>,

                     <&dispcc_dptx0_link_intf_clk>,

                     <&dispcc_dptx0_pixel0_clk>;

            clock-names = "core_iface",

                          "core_aux",

                          "ctrl_link",

                          "ctrl_link_iface",

                          "stream_pixel";

            assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>,

                              <&dispcc_mdss_dptx0_pixel0_clk_src>;

            assigned-clock-parents = <&mdss0_edp_phy 0>, <&mdss0_edp_phy 1>;

            phys = <&mdss0_edp_phy>;

            phy-names = "dp";

            operating-points-v2 = <&dp_opp_table>;

            power-domains = <&rpmhpd SA8775P_MMCX>;

            #sound-dai-cells = <0>;

            ports {

                #address-cells = <1>;

                #size-cells = <0>;

                port@0 {

                    reg = <0>;

                    mdss0_dp0_in: endpoint {

                        remote-endpoint = <&dpu_intf0_out>;

                    };

                };

                port@1 {

                   reg = <1>;

                   mdss0_dp_out: endpoint { };

                };

            };

            dp_opp_table: opp-table {

                compatible = "operating-points-v2";

                opp-160000000 {

                    opp-hz = /bits/ 64 <160000000>;

                    required-opps = <&rpmhpd_opp_low_svs>;

                };

                opp-270000000 {

                    opp-hz = /bits/ 64 <270000000>;

                    required-opps = <&rpmhpd_opp_svs>;

                };

                opp-540000000 {

                    opp-hz = /bits/ 64 <540000000>;

                    required-opps = <&rpmhpd_opp_svs_l1>;

                };

                opp-810000000 {

                    opp-hz = /bits/ 64 <810000000>;

                    required-opps = <&rpmhpd_opp_nom>;

                };

            };

        };

    };

...