Commit 40989bf0 authored by Dominik Kaszewski's avatar Dominik Kaszewski Committed by Alex Deucher
Browse files

drm/amd/display: Refactor and fix link_dpms info 



[Why]
get_ext_hdmi_settings contained a copy-paste error, assigning
both reg_num_6g and reg_num from dp0_ext_hdmi_6g_reg_num.

[How]
* Correctly assign reg_num from dp0_ext_hdmi_reg_num.
* Refactor and clean the function.

Reviewed-by: default avatarWenjing Liu <wenjing.liu@amd.com>
Signed-off-by: default avatarDominik Kaszewski <dominik.kaszewski@amd.com>
Signed-off-by: default avatarRay Wu <ray.wu@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a4f01bf7

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

+84 −81
Original line number Diff line number Diff line
@@ -223,16 +223,32 @@ void link_get_master_pipes_with_dpms_on(const struct dc_link *link, 
	}

}



static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,

		enum engine_id eng_id,

		struct ext_hdmi_settings *settings)

static struct ext_hdmi_settings create_ext_hdmi_settings(

		uint8_t address,

		uint8_t reg_num,

		uint8_t reg_num_6g,

		const struct i2c_reg_info *reg_settings,

		const struct i2c_reg_info *reg_settings_6g

)

{

	bool result = false;

	int i = 0;

	struct integrated_info *integrated_info =

			pipe_ctx->stream->ctx->dc_bios->integrated_info;

	struct ext_hdmi_settings result = {

		.slv_addr = address,

		.reg_num = reg_num,

		.reg_num_6g = reg_num_6g,

	};



	memcpy(result.reg_settings, reg_settings, sizeof(result.reg_settings));

	memcpy(result.reg_settings_6g, reg_settings_6g, sizeof(result.reg_settings_6g));

	return result;

}



	if (integrated_info == NULL)

static bool get_ext_hdmi_settings(

		const struct integrated_info *info,

		enum engine_id eng_id,

		struct ext_hdmi_settings *settings

)

{

	if (!settings || !info)

		return false;



	/*
@@ -242,82 +258,69 @@ static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx, 
	 */



	// Check if current bios contains ext Hdmi settings

	if (integrated_info->gpu_cap_info & 0x20) {

	if (!(info->gpu_cap_info & 0x20))

		return false;



	switch (eng_id) {

	case ENGINE_ID_DIGA:

			settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr;

			settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num;

			settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num;

			memmove(settings->reg_settings,

					integrated_info->dp0_ext_hdmi_reg_settings,

					sizeof(integrated_info->dp0_ext_hdmi_reg_settings));

			memmove(settings->reg_settings_6g,

					integrated_info->dp0_ext_hdmi_6g_reg_settings,

					sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings));

			result = true;

		*settings = create_ext_hdmi_settings(

				info->dp0_ext_hdmi_slv_addr,

				info->dp0_ext_hdmi_reg_num,

				info->dp0_ext_hdmi_6g_reg_num,

				info->dp0_ext_hdmi_reg_settings,

				info->dp0_ext_hdmi_6g_reg_settings

		);

		break;

	case ENGINE_ID_DIGB:

			settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr;

			settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num;

			settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num;

			memmove(settings->reg_settings,

					integrated_info->dp1_ext_hdmi_reg_settings,

					sizeof(integrated_info->dp1_ext_hdmi_reg_settings));

			memmove(settings->reg_settings_6g,

					integrated_info->dp1_ext_hdmi_6g_reg_settings,

					sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings));

			result = true;

		*settings = create_ext_hdmi_settings(

				info->dp1_ext_hdmi_slv_addr,

				info->dp1_ext_hdmi_reg_num,

				info->dp1_ext_hdmi_6g_reg_num,

				info->dp1_ext_hdmi_reg_settings,

				info->dp1_ext_hdmi_6g_reg_settings

		);

		break;

	case ENGINE_ID_DIGC:

			settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr;

			settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num;

			settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num;

			memmove(settings->reg_settings,

					integrated_info->dp2_ext_hdmi_reg_settings,

					sizeof(integrated_info->dp2_ext_hdmi_reg_settings));

			memmove(settings->reg_settings_6g,

					integrated_info->dp2_ext_hdmi_6g_reg_settings,

					sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings));

			result = true;

		*settings = create_ext_hdmi_settings(

				info->dp2_ext_hdmi_slv_addr,

				info->dp2_ext_hdmi_reg_num,

				info->dp2_ext_hdmi_6g_reg_num,

				info->dp2_ext_hdmi_reg_settings,

				info->dp2_ext_hdmi_6g_reg_settings

		);

		break;

	case ENGINE_ID_DIGD:

			settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr;

			settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num;

			settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num;

			memmove(settings->reg_settings,

					integrated_info->dp3_ext_hdmi_reg_settings,

					sizeof(integrated_info->dp3_ext_hdmi_reg_settings));

			memmove(settings->reg_settings_6g,

					integrated_info->dp3_ext_hdmi_6g_reg_settings,

					sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings));

			result = true;

		*settings = create_ext_hdmi_settings(

				info->dp3_ext_hdmi_slv_addr,

				info->dp3_ext_hdmi_reg_num,

				info->dp3_ext_hdmi_6g_reg_num,

				info->dp3_ext_hdmi_reg_settings,

				info->dp3_ext_hdmi_6g_reg_settings

		);

		break;

	default:

			break;

		return false;

	}



		if (result == true) {

	// Validate settings from bios integrated info table

			if (settings->slv_addr == 0)

				return false;

			if (settings->reg_num > 9)

				return false;

			if (settings->reg_num_6g > 3)

	if (

			!settings->slv_addr

			|| settings->reg_num > ARRAY_SIZE(settings->reg_settings)

			|| settings->reg_num_6g > ARRAY_SIZE(settings->reg_settings_6g)

	) {

		return false;

	}



			for (i = 0; i < settings->reg_num; i++) {

	for (size_t i = 0; i < settings->reg_num; i++) {

		if (settings->reg_settings[i].i2c_reg_index > 0x20)

			return false;

	}



			for (i = 0; i < settings->reg_num_6g; i++) {

	for (size_t i = 0; i < settings->reg_num_6g; i++) {

		if (settings->reg_settings_6g[i].i2c_reg_index > 0x20)

			return false;

	}

		}

	}



	return result;

	return true;

}



static bool write_i2c(
@@ -1792,7 +1795,7 @@ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) 
			/* DP159, Retimer settings */

			eng_id = pipe_ctx->stream_res.stream_enc->id;



			if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) {

			if (get_ext_hdmi_settings(stream->ctx->dc_bios->integrated_info, eng_id, &settings)) {

				write_i2c_retimer_setting(link, is_vga_mode, is_over_340mhz, &settings);

			} else {

				write_i2c_default_retimer_setting(link, is_vga_mode, is_over_340mhz);
@@ -2221,7 +2224,7 @@ void link_set_dpms_off(struct pipe_ctx *pipe_ctx) 
			false);

		if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {

			/* DP159, Retimer settings */

			if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings))

			if (get_ext_hdmi_settings(stream->ctx->dc_bios->integrated_info, eng_id, &settings))

				write_i2c_retimer_setting(link, false, false, &settings);

			else

				write_i2c_default_retimer_setting(link, false, false);