Commit 40c687a4 authored by Jan Petrous (OSS)'s avatar Jan Petrous (OSS) Committed by Shawn Guo
Browse files

arm64: dts: freescale: Add GMAC Ethernet for S32G2 EVB and RDB2 and S32G3 RDB3 



Add support for the Ethernet connection over GMAC controller connected to
the Micrel KSZ9031 Ethernet RGMII PHY located on the boards.

The mentioned GMAC controller is one of two network controllers
embedded on the NXP Automotive SoCs S32G2 and S32G3.

The supported boards:
 * EVB:  S32G-VNP-EVB with S32G2 SoC
 * RDB2: S32G-VNP-RDB2
 * RDB3: S32G-VNP-RDB3

Tested-by: default avatarEnric Balletbo i Serra <eballetb@redhat.com>
Signed-off-by: default avatarJan Petrous (OSS) <jan.petrous@oss.nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent cb927379

arch/arm64/boot/dts/freescale/s32g2.dtsi

+57 −1
Original line number Diff line number Diff line
@@ -3,7 +3,7 @@ 
 * NXP S32G2 SoC family

 *

 * Copyright (c) 2021 SUSE LLC

 * Copyright 2017-2021, 2024 NXP

 * Copyright 2017-2021, 2024-2025 NXP

 */



#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -727,6 +727,62 @@ usdhc0: mmc@402f0000 { 
			status = "disabled";

		};



		gmac0: ethernet@4033c000 {

			compatible = "nxp,s32g2-dwmac";

			reg = <0x4033c000 0x2000>, /* gmac IP */

			      <0x4007c004 0x4>;    /* GMAC_0_CTRL_STS */

			interrupt-parent = <&gic>;

			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "macirq";

			snps,mtl-rx-config = <&mtl_rx_setup>;

			snps,mtl-tx-config = <&mtl_tx_setup>;

			status = "disabled";



			mtl_rx_setup: rx-queues-config {

				snps,rx-queues-to-use = <5>;



				queue0 {

				};



				queue1 {

				};



				queue2 {

				};



				queue3 {

				};



				queue4 {

				};

			};



			mtl_tx_setup: tx-queues-config {

				snps,tx-queues-to-use = <5>;



				queue0 {

				};



				queue1 {

				};



				queue2 {

				};



				queue3 {

				};



				queue4 {

				};

			};



			gmac0mdio: mdio {

				compatible = "snps,dwmac-mdio";

				#address-cells = <1>;

				#size-cells = <0>;

			};

		};



		gic: interrupt-controller@50800000 {

			compatible = "arm,gic-v3";

			reg = <0x50800000 0x10000>,

arch/arm64/boot/dts/freescale/s32g274a-evb.dts

+17 −1
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT

/*

 * Copyright (c) 2021 SUSE LLC

 * Copyright 2019-2021, 2024 NXP

 * Copyright 2019-2021, 2024-2025 NXP

 */



/dts-v1/;
@@ -14,6 +14,7 @@ / { 
	compatible = "nxp,s32g274a-evb", "nxp,s32g2";



	aliases {

		ethernet0 = &gmac0;

		serial0 = &uart0;

	};
@@ -43,3 +44,18 @@ &usdhc0 { 
	no-1-8-v;

	status = "okay";

};



&gmac0 {

	clocks = <&clks 24>, <&clks 19>, <&clks 18>, <&clks 15>;

	clock-names = "stmmaceth", "tx", "rx", "ptp_ref";

	phy-mode = "rgmii-id";

	phy-handle = <&rgmiiaphy4>;

	status = "okay";

};



&gmac0mdio {

	/* KSZ 9031 on RGMII */

	rgmiiaphy4: ethernet-phy@4 {

		reg = <4>;

	};

};

arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts

+16 −0
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ / { 
	compatible = "nxp,s32g274a-rdb2", "nxp,s32g2";



	aliases {

		ethernet0 = &gmac0;

		serial0 = &uart0;

		serial1 = &uart1;

	};
@@ -77,3 +78,18 @@ &usdhc0 { 
	no-1-8-v;

	status = "okay";

};



&gmac0 {

	clocks = <&clks 24>, <&clks 19>, <&clks 18>, <&clks 15>;

	clock-names = "stmmaceth", "tx", "rx", "ptp_ref";

	phy-mode = "rgmii-id";

	phy-handle = <&rgmiiaphy1>;

	status = "okay";

};



&gmac0mdio {

	/* KSZ 9031 on RGMII */

	rgmiiaphy1: ethernet-phy@1 {

		reg = <1>;

	};

};

arch/arm64/boot/dts/freescale/s32g3.dtsi

+57 −1
Original line number Diff line number Diff line 
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)

/*

 * Copyright 2021-2024 NXP

 * Copyright 2021-2025 NXP

 *

 * Authors: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

 *          Ciprian Costea <ciprianmarian.costea@nxp.com>
@@ -804,6 +804,62 @@ usdhc0: mmc@402f0000 { 
			status = "disabled";

		};



		gmac0: ethernet@4033c000 {

			compatible = "nxp,s32g2-dwmac";

			reg = <0x4033c000 0x2000>, /* gmac IP */

			      <0x4007c004 0x4>;    /* GMAC_0_CTRL_STS */

			interrupt-parent = <&gic>;

			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "macirq";

			snps,mtl-rx-config = <&mtl_rx_setup>;

			snps,mtl-tx-config = <&mtl_tx_setup>;

			status = "disabled";



			mtl_rx_setup: rx-queues-config {

				snps,rx-queues-to-use = <5>;



				queue0 {

				};



				queue1 {

				};



				queue2 {

				};



				queue3 {

				};



				queue4 {

				};

			};



			mtl_tx_setup: tx-queues-config {

				snps,tx-queues-to-use = <5>;



				queue0 {

				};



				queue1 {

				};



				queue2 {

				};



				queue3 {

				};



				queue4 {

				};

			};



			gmac0mdio: mdio {

				compatible = "snps,dwmac-mdio";

				#address-cells = <1>;

				#size-cells = <0>;

			};

		};



		swt8: watchdog@40500000 {

			compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";

			reg = <40500000 0x1000>;

arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts

+17 −1
Original line number Diff line number Diff line 
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)

/*

 * Copyright 2021-2024 NXP

 * Copyright 2021-2025 NXP

 *

 * NXP S32G3 Reference Design Board 3 (S32G-VNP-RDB3)

 */
@@ -15,6 +15,7 @@ / { 
	compatible = "nxp,s32g399a-rdb3", "nxp,s32g3";



	aliases {

		ethernet0 = &gmac0;

		mmc0 = &usdhc0;

		serial0 = &uart0;

		serial1 = &uart1;
@@ -93,3 +94,18 @@ &usdhc0 { 
	disable-wp;

	status = "okay";

};



&gmac0 {

	clocks = <&clks 24>, <&clks 19>, <&clks 18>, <&clks 15>;

	clock-names = "stmmaceth", "tx", "rx", "ptp_ref";

	phy-mode = "rgmii-id";

	phy-handle = <&rgmiiaphy1>;

	status = "okay";

};



&gmac0mdio {

	/* KSZ 9031 on RGMII */

	rgmiiaphy1: ethernet-phy@1 {

		reg = <1>;

	};

};