Unverified Commit 40e09ebd authored by Jesse Taube's avatar Jesse Taube Committed by Palmer Dabbelt
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RISC-V: hwprobe: Document unaligned vector perf key 



Document key for reporting the speed of unaligned vector accesses.
The descriptions are the same as the scalar equivalent values.

Signed-off-by: default avatarJesse Taube <jesse@rivosinc.com>
Reviewed-by: default avatarCharlie Jenkins <charlie@rivosinc.com>
Link: https://lore.kernel.org/r/20241017-jesse_unaligned_vector-v10-6-5b33500160f8@rivosinc.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent e7c9d66e

Documentation/arch/riscv/hwprobe.rst

+16 −0
Original line number Diff line number Diff line
@@ -274,3 +274,19 @@ The following keys are defined: 
  represent the highest userspace virtual address usable.



* :c:macro:`RISCV_HWPROBE_KEY_TIME_CSR_FREQ`: Frequency (in Hz) of `time CSR`.



* :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF`: An enum value describing the

     performance of misaligned vector accesses on the selected set of processors.



  * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNKNOWN`: The performance of misaligned

    vector accesses is unknown.



  * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_SLOW`: 32-bit misaligned accesses using vector

    registers are slower than the equivalent quantity of byte accesses via vector registers.

    Misaligned accesses may be supported directly in hardware, or trapped and emulated by software.



  * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_FAST`: 32-bit misaligned accesses using vector

    registers are faster than the equivalent quantity of byte accesses via vector registers.



  * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED`: Misaligned vector accesses are

    not supported at all and will generate a misaligned address fault.