Commit 411389d2 authored by Tejas Upadhyay's avatar Tejas Upadhyay
Browse files

drm/xe/pat: define coh_mode 2way 



Defining 2way (two-way coherency) is critical for
Xe3p_LPG (Nova Lake P) platforms to support L2 flush
optimization safely.

This mode allows the driver to skip certain manual cache
flushes (L2 flush optimization) without risking memory
corruption because the hardware ensures the most recent
data is visible to both entities.

Reviewed-by: default avatarMatthew Auld <matthew.auld@intel.com>
Link: https://patch.msgid.link/20260305121902.1892593-8-tejas.upadhyay@intel.com


Signed-off-by: default avatarTejas Upadhyay <tejas.upadhyay@intel.com>
parent 4e7ebff6

drivers/gpu/drm/xe/xe_pat.c

+7 −7
Original line number Diff line number Diff line
@@ -92,7 +92,7 @@ struct xe_pat_ops { 
};



static const struct xe_pat_table_entry xelp_pat_table[] = {

	[0] = { XELP_PAT_WB, XE_COH_AT_LEAST_1WAY },

	[0] = { XELP_PAT_WB, XE_COH_1WAY },

	[1] = { XELP_PAT_WC, XE_COH_NONE },

	[2] = { XELP_PAT_WT, XE_COH_NONE },

	[3] = { XELP_PAT_UC, XE_COH_NONE },
@@ -102,19 +102,19 @@ static const struct xe_pat_table_entry xehpc_pat_table[] = { 
	[0] = { XELP_PAT_UC, XE_COH_NONE },

	[1] = { XELP_PAT_WC, XE_COH_NONE },

	[2] = { XELP_PAT_WT, XE_COH_NONE },

	[3] = { XELP_PAT_WB, XE_COH_AT_LEAST_1WAY },

	[3] = { XELP_PAT_WB, XE_COH_1WAY },

	[4] = { XEHPC_PAT_CLOS(1) | XELP_PAT_WT, XE_COH_NONE },

	[5] = { XEHPC_PAT_CLOS(1) | XELP_PAT_WB, XE_COH_AT_LEAST_1WAY },

	[5] = { XEHPC_PAT_CLOS(1) | XELP_PAT_WB, XE_COH_1WAY },

	[6] = { XEHPC_PAT_CLOS(2) | XELP_PAT_WT, XE_COH_NONE },

	[7] = { XEHPC_PAT_CLOS(2) | XELP_PAT_WB, XE_COH_AT_LEAST_1WAY },

	[7] = { XEHPC_PAT_CLOS(2) | XELP_PAT_WB, XE_COH_1WAY },

};



static const struct xe_pat_table_entry xelpg_pat_table[] = {

	[0] = { XELPG_PAT_0_WB, XE_COH_NONE },

	[1] = { XELPG_PAT_1_WT, XE_COH_NONE },

	[2] = { XELPG_PAT_3_UC, XE_COH_NONE },

	[3] = { XELPG_PAT_0_WB | XELPG_2_COH_1W, XE_COH_AT_LEAST_1WAY },

	[4] = { XELPG_PAT_0_WB | XELPG_3_COH_2W, XE_COH_AT_LEAST_1WAY },

	[3] = { XELPG_PAT_0_WB | XELPG_2_COH_1W, XE_COH_1WAY },

	[4] = { XELPG_PAT_0_WB | XELPG_3_COH_2W, XE_COH_2WAY },

};



/*
@@ -147,7 +147,7 @@ static const struct xe_pat_table_entry xelpg_pat_table[] = { 
			REG_FIELD_PREP(XE2_L3_POLICY, l3_policy) | \

			REG_FIELD_PREP(XE2_L4_POLICY, l4_policy) | \

			REG_FIELD_PREP(XE2_COH_MODE, __coh_mode), \

		.coh_mode = __coh_mode ? XE_COH_AT_LEAST_1WAY : XE_COH_NONE, \

		.coh_mode = __coh_mode ? __coh_mode : XE_COH_NONE, \

		.valid = 1 \

	}

drivers/gpu/drm/xe/xe_pat.h

+3 −2
Original line number Diff line number Diff line
@@ -29,7 +29,8 @@ struct xe_pat_table_entry { 
	 * @coh_mode: The GPU coherency mode that @value maps to.

	 */

#define XE_COH_NONE		1

#define XE_COH_AT_LEAST_1WAY 2

#define XE_COH_1WAY		2

#define XE_COH_2WAY		3

	u16 coh_mode;



	/**

drivers/gpu/drm/xe/xe_vm.c

+1 −1
Original line number Diff line number Diff line
@@ -3465,7 +3465,7 @@ static int vm_bind_ioctl_check_args(struct xe_device *xe, struct xe_vm *vm, 
			goto free_bind_ops;

		}



		if (XE_WARN_ON(coh_mode > XE_COH_AT_LEAST_1WAY)) {

		if (XE_WARN_ON(coh_mode > XE_COH_2WAY)) {

			err = -EINVAL;

			goto free_bind_ops;

		}

drivers/gpu/drm/xe/xe_vm_madvise.c

+1 −1
Original line number Diff line number Diff line
@@ -309,7 +309,7 @@ static bool madvise_args_are_sane(struct xe_device *xe, const struct drm_xe_madv 
		if (XE_IOCTL_DBG(xe, !coh_mode))

			return false;



		if (XE_WARN_ON(coh_mode > XE_COH_AT_LEAST_1WAY))

		if (XE_WARN_ON(coh_mode > XE_COH_2WAY))

			return false;



		if (XE_IOCTL_DBG(xe, args->pat_index.pad))