Commit 41197eb5 authored by Chen Wang's avatar Chen Wang Committed by Philipp Zabel
Browse files

dt-bindings: reset: sophgo: support SG2042 



Add bindings for the reset generator on the SOPHGO SG2042 RISC-V SoC.

Signed-off-by: default avatarChen Wang <unicorn_wang@outlook.com>
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: default avatarInochi Amaoto <inochiama@outlook.com>
Link: https://lore.kernel.org/r/35c348437b6e18972ccaf90d9c38040caccd1f11.1706577450.git.unicorn_wang@outlook.com


Signed-off-by: default avatarPhilipp Zabel <p.zabel@pengutronix.de>
parent b401b621

Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml

0 → 100644
+35 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/reset/sophgo,sg2042-reset.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Sophgo SG2042 SoC Reset Controller



maintainers:

  - Chen Wang <unicorn_wang@outlook.com>



properties:

  compatible:

    const: sophgo,sg2042-reset



  reg:

    maxItems: 1



  "#reset-cells":

    const: 1



required:

  - compatible

  - reg

  - "#reset-cells"



additionalProperties: false



examples:

  - |

    rstgen: reset-controller@c00 {

        compatible = "sophgo,sg2042-reset";

        reg = <0xc00 0xc>;

        #reset-cells = <1>;

    };

include/dt-bindings/reset/sophgo,sg2042-reset.h

0 → 100644
+87 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */

/*

 * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved.

 */



#ifndef __DT_BINDINGS_RESET_SOPHGO_SG2042_H_

#define __DT_BINDINGS_RESET_SOPHGO_SG2042_H_



#define RST_MAIN_AP			0

#define RST_RISCV_CPU			1

#define RST_RISCV_LOW_SPEED_LOGIC	2

#define RST_RISCV_CMN			3

#define RST_HSDMA			4

#define RST_SYSDMA			5

#define RST_EFUSE0			6

#define RST_EFUSE1			7

#define RST_RTC				8

#define RST_TIMER			9

#define RST_WDT				10

#define RST_AHB_ROM0			11

#define RST_AHB_ROM1			12

#define RST_I2C0			13

#define RST_I2C1			14

#define RST_I2C2			15

#define RST_I2C3			16

#define RST_GPIO0			17

#define RST_GPIO1			18

#define RST_GPIO2			19

#define RST_PWM				20

#define RST_AXI_SRAM0			21

#define RST_AXI_SRAM1			22

#define RST_SF0				23

#define RST_SF1				24

#define RST_LPC				25

#define RST_ETH0			26

#define RST_EMMC			27

#define RST_SD				28

#define RST_UART0			29

#define RST_UART1			30

#define RST_UART2			31

#define RST_UART3			32

#define RST_SPI0			33

#define RST_SPI1			34

#define RST_DBG_I2C			35

#define RST_PCIE0			36

#define RST_PCIE1			37

#define RST_DDR0			38

#define RST_DDR1			39

#define RST_DDR2			40

#define RST_DDR3			41

#define RST_FAU0			42

#define RST_FAU1			43

#define RST_FAU2			44

#define RST_RXU0			45

#define RST_RXU1			46

#define RST_RXU2			47

#define RST_RXU3			48

#define RST_RXU4			49

#define RST_RXU5			50

#define RST_RXU6			51

#define RST_RXU7			52

#define RST_RXU8			53

#define RST_RXU9			54

#define RST_RXU10			55

#define RST_RXU11			56

#define RST_RXU12			57

#define RST_RXU13			58

#define RST_RXU14			59

#define RST_RXU15			60

#define RST_RXU16			61

#define RST_RXU17			62

#define RST_RXU18			63

#define RST_RXU19			64

#define RST_RXU20			65

#define RST_RXU21			66

#define RST_RXU22			67

#define RST_RXU23			68

#define RST_RXU24			69

#define RST_RXU25			70

#define RST_RXU26			71

#define RST_RXU27			72

#define RST_RXU28			73

#define RST_RXU29			74

#define RST_RXU30			75

#define RST_RXU31			76



#endif /* __DT_BINDINGS_RESET_SOPHGO_SG2042_H_ */